Radar Memory Sub-Bank Switching Reduction
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Solution Overview
Problem
Radar systems face high power consumption and heat generation issues, particularly in high-temperature environments, due to increased static leakage currents, which can lead to increased costs and inefficiencies in memory operations.
Innovation Solution
The implementation of a memory system with a first and second portion, and memory control circuitry that rearranges sample data to reduce memory sub-bank switching, allowing for linear memory read operations and minimizing inrush current events by controlling power-up sequences and using retention modes to conserve energy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory sub-bank switching is performed to store radar data, then data storage capacity is improved, but power consumption increases due to inrush currents
Solution Approach 1:
The patent applies preliminary action by pre-organizing radar data into contiguous subsets within the first memory portion before storage operations. This pre-arrangement enables subsequent read operations to access entire data sets without triggering sub-bank switching, thereby preventing inrush currents while maintaining adequate storage capacity through the two-portion memory architecture
2Reliability
If memory operations are performed in high-temperature environments, then radar system operation is maintained, but static leakage currents increase causing higher power consumption
Solution Approach 1:
The patent segments memory operations into two distinct portions: the first memory portion for contiguous data storage and the second memory portion for additional data. This segmentation allows the system to perform efficient read operations from the first portion without sub-bank switching, reducing power consumption in high-temperature environments while maintaining reliable radar operation
Solution Approach 2:
The patent changes the organizational parameters of data storage by arranging data subsets contiguously within the first memory portion rather than using traditional sub-bank distribution. This parameter change reduces the frequency of sub-bank switching operations, thereby reducing static leakage current effects and power consumption in high-temperature environments
3Use of energy by moving object
If sub-bank transitions are minimized, then power consumption is reduced, but data access flexibility may be limited
Solution Approach 1:
The patent resolves the contradiction between power consumption and data access flexibility by introducing a dimensional organization within the first memory portion. Data from multiple radar chirps are arranged contiguously along one dimension, enabling efficient linear read operations without sub-bank transitions, while the two-portion memory architecture provides additional dimensional flexibility for different access patterns
Data Source
AI summary
An example device includes a memory that includes a first portion and a second portion, memory control circuitry structured to receive a first set of data associated with a first radar chirp, receive a second set of data associated with a second radar chirp, store a first subset of the first set of data in the first portion of the memory, store a first subset of the second set of data in the first portion of the memory adjacent to the first subset of the first set of data, and store a second subset of the first set of data and a second subset of the second set of data in the second portion of the memory.