Radar Signal Compression for On-Chip Memory-Limited FMCW Systems
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Solution Overview
Problem
The limited on-chip memory in embedded FMCW radar systems constrains the storage of radar data, limiting the resolution and capabilities of the systems, as current memory sizes are insufficient to handle increasing resolution demands in automotive applications.
Innovation Solution
The implementation of memory compression techniques such as block floating point (BFP), bit packing (PAC), and order k exponential Golomb (EG) compression after the range FFT, which reduce the bit width of radar data while maintaining dynamic range and accuracy, allowing for more data to be stored in the same memory size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If larger memory capacity is included in radar transceiver ICs, then the amount of radar data that can be stored increases, but die size and cost increase
Solution Approach 1:
The patent applies parameter changes by transforming the data representation format from full-precision complex numbers to compressed formats (such as magnitude-phase representation or reduced-bit quantization). This changes the fundamental parameters of data storage, allowing more data to be stored in the same memory capacity without increasing die size.
Solution Approach 2:
The patent extracts only the essential information needed for radar signal processing by separating magnitude and phase components, or by retaining only significant bits after range FFT processing. This extraction approach reduces the storage requirements while maintaining the necessary data fidelity for velocity and angle calculations.
2Quantity of substance
If larger memory capacity is included in radar transceiver ICs, then the amount of radar data that can be stored increases, but cost increases
Solution Approach 1:
By changing the data representation parameters to compressed formats, the patent reduces memory requirements, which directly lowers manufacturing costs associated with larger memory arrays, while maintaining the same functional capabilities.
3Measurement precision
If on-chip memory size is limited, then die size and cost are controlled, but the resolution and capabilities of the radar system are constrained
Solution Approach 1:
The patent changes the data storage parameters by implementing compression algorithms that reduce the bits required per data point. This allows the same memory capacity to store more data points, thereby improving resolution in range, velocity, and angle measurements without requiring additional memory resources.
Solution Approach 2:
The patent segments the radar data processing into stages (range FFT, velocity processing, angle processing) and applies compression at intermediate stages. This segmentation allows for efficient memory utilization at each processing stage while maintaining the ability to achieve high resolution in the final output.
Data Source
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AI summary
In described examples, a radar system (2000) includes a compression component (2025) configured to compress blocks of range values to generate compressed blocks of range values, and a radar data memory (2026) configured to store compressed blocks of range values generated by the compression component (2025).