Self-Aligned Radhard VDMOS via Sacrificial Poly Mask
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Solution Overview
Problem
Vertical Power MOSFETs (VDMOS) in space and military applications face severe degradation and potential destruction due to Single Event Burnout from heavy ion bombardment, with existing radiation hardening methods either increasing the risk of parasitic NPN transistor turn-on or degrading the device's On Resistance.
Innovation Solution
A manufacturing method involving self-aligned implanted and diffused layers using a sacrificial polysilicon masking layer, followed by late gate oxide formation, and a graded epitaxial doping profile to minimize secondary breakdown and maintain low On Resistance, ensuring precise alignment and improved radiation resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the doping of the UIS implant layer is increased to reduce the propensity of the parasitic NPN to turn on, then the radiation resistance is improved, but the doping can reach the silicon-silicon dioxide interface and cause a sharp increase in threshold voltage, making the MOSFET dead at that location
Solution Approach 1:
The patent divides the implantation process into multiple segments: first forming a sacrificial polysilicon layer to define the source region, then performing the UIS implantation through openings in this sacrificial layer. This segmentation allows precise control of the implantation depth and lateral distribution, ensuring the UIS doping is concentrated where needed without reaching the gate oxide interface
Solution Approach 2:
The sacrificial polysilicon layer is formed in advance before the UIS implantation. This preliminary structure serves as a mask that pre-defines the implantation region, allowing the subsequent UIS doping to be automatically confined to the correct lateral position underneath the source, preventing it from reaching the gate oxide
2Reliability
If the placement of the UIS layer is not perfect to achieve high doping levels, then the radiation resistance is improved, but the alignment variations can cause uneven turn-on of the parasitic NPN transistor and lead to device destruction
Solution Approach 1:
The sacrificial polysilicon layer serves as a self-aligning mask that automatically defines the implantation region. The UIS implantation is performed through openings in this sacrificial layer, which is itself positioned relative to the source region. This self-service approach eliminates the need for separate alignment steps, as the sacrificial layer's position relative to the source automatically ensures correct UIS placement
Solution Approach 2:
The sacrificial polysilicon layer acts as an intermediary structure that mediates the alignment between the source region and the UIS implantation. By using this intermediate mask layer, the patent indirectly achieves precise alignment without requiring direct measurement or adjustment, as the sacrificial layer's geometry and position automatically transfer the correct spatial relationship
3Ease of manufacture
If conventional gate oxide formation is performed early in the process, then the manufacturing process is simplified, but the gate oxide degrades under high temperature dopant implantation and diffusion steps, reducing radiation resistance
Solution Approach 1:
The gate oxide formation is delayed until after all high-temperature dopant implantation and diffusion steps are completed. This timing decision ensures the gate oxide is not exposed to degrading conditions, preserving its quality and the device's radiation resistance. The sacrificial polysilicon layer enables this delayed gate formation by serving as the alignment reference for all subsequent steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in radiation-hardened VDMOS transistors with enhanced secondary breakdown voltage and reduced On Resistance, effectively mitigating Single Event Burnout and maintaining performance under heavy ion bombardment.
Implementation Method 1
self-aligned implanted and diffused layers using a sacrificial polysilicon masking layer
Implementation Method 2
late gate oxide formation
Implementation Method 3
graded epitaxial doping profile
Implementation Method 4
implanted and diffused layers
Implementation Method 5
implanted and diffused layers
Data Source
AI summary
A Vertical Power MOSFET (VDMOS) device with special features that enable the Power MOSFET or IGBT device to withstand harsh radiation environments and the process of making such a device is described. All implanted and diffused layers are “self aligned” to a “Sacrificial Poly” layer, which later on is removed, preparing the wafers for a “late gate” oxide to be grown. A starting material with graded doping profile in the epitaxial layer on the substrate is shown to increase the SEB capability of the Power MOSFET.