Radial Solder Ball Pattern for High-Density PCB Routing
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Solution Overview
Problem
Conventional printed circuit boards face limitations in connection density due to physical and electrical constraints, which restrict the number of connections that can be made near each other, especially with the increasing complexity and smaller size of chips, leading to wasted space and reduced I/O routing capabilities.
Innovation Solution
A radial star ball pattern is implemented on the printed circuit board, rearranging the package ball pattern in the middle span region to optimize differential pair routing, increasing the routable I/O count without expanding the package form factor by creating larger breakout areas and redistributing ground vias, allowing for more efficient signal tracing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional grid ball patterns are used on printed circuit boards, then manufacturing is simpler and easier, but connection density is limited due to physical and electrical constraints between nearby connections
Solution Approach 1:
The patent transitions from a symmetric grid ball pattern to an asymmetric radial star ball pattern. The radial pattern positions solder balls at varying distances from the center along radial lines, creating asymmetric spacing that optimizes routing paths. This allows differential pairs to be routed more efficiently through the board, increasing connection density while managing the complexity of signal tracing through strategic asymmetric placement rather than uniform distribution
Solution Approach 2:
The patent moves from a two-dimensional grid arrangement to a radial pattern that effectively utilizes spatial dimensions differently. By organizing balls along radial lines from a central point rather than in orthogonal rows and columns, the design creates more varied path lengths and routing options in the plane, enabling higher density connections without increasing the physical footprint of the package
2Area of moving object
If chip size is reduced to lower cost and improve performance, then integration is improved, but surface area for external connections is reduced
Solution Approach 1:
The radial star ball pattern reorganizes the connection layout to maximize the utilization of available surface area. By arranging balls radially from a center point rather than in a grid, the design creates more efficient use of the circular or square chip footprint, allowing more connection points to be packed into the same or smaller area while maintaining proper spacing for routing
3Quantity of substance
If more connections are made near each other on the printed circuit board, then connection density increases, but physical and electrical separation between connections becomes insufficient
Solution Approach 1:
The asymmetric radial pattern creates variable spacing between adjacent balls, with some pairs closer and others farther apart. This asymmetric distribution allows routing designs that account for signal integrity requirements by providing adequate separation for high-speed differential pairs while allowing tighter spacing for less critical connections, thus maintaining reliability while achieving higher overall density
Solution Approach 2:
Different regions of the radial pattern provide different connection densities and spacing characteristics. Areas requiring higher signal integrity can be designed with larger radial spacing, while other areas can accommodate tighter packing. This local optimization of spacing quality allows the overall design to achieve high density while maintaining necessary separation for reliable signal transmission in critical areas
Data Source
AI summary
A radial solder ball pattern is described for a printed circuit board and for a chip to be attached to the printed circuit board is described. In one example, the pattern comprises a central power connector area having a plurality of power connectors to provide power to an attached chip, a signal area having a plurality of signal connectors to communicate signals to the attached chip, an edge area surrounding the signal area and the central power connector area, and a plurality of traces each coupled to a signal connector, the traces extending from the respective coupled signal connector away from the central power connector to connect to an external component, wherein the signal connectors are placed in rows, the rows having a greater separation near the edge area than near the central area.