Radiation Detector Conductive Buffer Layer Charge Dissipation
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Solution Overview
Problem
The existing radiation detectors with dummy patterns in buffer regions between pixel and peripheral circuit regions are prone to dielectric breakdown due to charge-up, affecting their performance and reliability.
Innovation Solution
A radiation detector design that includes a first intermediate region with a conductive layer supplied with a potential, arranged between the pixel and peripheral circuit regions, to prevent charge accumulation and reduce the risk of dielectric breakdown, while maintaining the flatness of interlayer insulating layers through CMP processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dummy pattern is arranged in the buffer region to planarize the interlayer insulating film by CMP, then the flatness of the interlayer insulating film is improved, but the dummy pattern may be charged up by radiation and cause dielectric breakdown
Solution Approach 1:
The patent introduces a conductive layer as an intermediary between the dummy pattern and the insulating layer. This conductive layer acts as a charge dissipation path, allowing accumulated radiation-induced charges to be safely discharged to ground potential, thereby preventing dielectric breakdown while maintaining the dummy pattern's planarization function
Solution Approach 2:
The conductive layer is maintained at ground potential through connection to a ground node. By keeping the conductive layer at a fixed potential, the patent prevents potential differences that would lead to charge accumulation and dielectric breakdown, while still allowing the dummy pattern to function for CMP planarization
2Object-affected harmful factors
If the distance between pixel region and peripheral circuit region is increased to prevent radiation spread, then radiation interference is reduced, but the chip area increases
Solution Approach 1:
The buffer region with conductive layer serves as an intermediary zone between the pixel region and peripheral circuit region. This intermediate structure provides radiation shielding and charge management functionality, allowing the regions to be closer together while preventing harmful radiation spread and charge accumulation
3Area of stationary object
If wiring portions are miniaturized to reduce chip size, then chip area is reduced, but CMP polishing rate differences between regions increase
Solution Approach 1:
The patent applies different patterns (dummy patterns in buffer regions) to different local areas of the chip. These localized dummy patterns compensate for polishing rate differences in specific regions without affecting the overall miniaturization of wiring portions, thereby maintaining both small chip size and uniform interlayer insulating film thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses dielectric breakdown and dark current generation, enhancing the radiation detector's performance and manufacturing yield by ensuring the conductive layer does not charge up and discharge radiation-induced charges, thereby improving the detector's sensitivity and reliability.
Implementation Method 1
the first conductive layer is configured to be supplied with a first potential... effectively suppresses dielectric breakdown and dark current generation, enhancing the radiation detector's performance and manufacturing yield by ensuring the conductive layer does not charge up and discharge radiation-induced charges
Implementation Method 2
a transistor that outputs a signal corresponding to a charge accumulated in the radiation detection element
Data Source
AI summary
A radiation detector includes a pixel region in which a plurality of pixels is arranged, a peripheral circuit region in which a signal processing circuit that processes a signal from the plurality of pixels is provided, and a first intermediate region arranged between the pixel region and the peripheral circuit region, wherein the first intermediate region includes a first conductive layer arranged in contact with the insulating layer, and wherein the first conductive layer is configured to be supplied with a predetermined potential.