Radiation-Hardened Interleaved ADC Calibration With Three-Point Timing

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Solution Overview

Problem

Time-interleaved analog-to-digital converters (ADCs) face challenges in calibration due to imprecise time derivative approximation, leading to error propagation and system failure, especially under radiation conditions causing single-event upsets (SEUs) and heavy ion effects, and require increasing complexity and cost to meet high sampling frequencies and resolution demands.

Innovation Solution

The implementation of a three-point calibration method for time-interleaved ADCs, which includes additional registers and computational elements to estimate a more precise time derivative, reducing error propagation and enhancing calibration efficiency, and the use of a clamped watchdog method to mitigate errors and reset values, thereby improving resilience to radiation effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional two-point calibration method is used, then circuit complexity is low, but time derivative approximation is imprecise leading to error propagation and calibration divergence

Engineering Contradiction:
Improvetime derivative approximation precisionVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The calibration process is segmented into multiple sampling points (first, second, and third time points) rather than using a simple two-point method. This segmentation allows for more precise time derivative approximation by capturing the signal behavior across multiple intervals, thereby improving measurement precision without excessively increasing circuit complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an additional time dimension by sampling at three distinct time points (k-1, k, k+1) instead of two. This dimensional expansion enables more accurate derivative calculation through central difference approximation, resolving the contradiction between precision and complexity by adding temporal resolution rather than spatial circuit elements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If calibration is performed under radiation conditions, then ADC can operate in harsh environments, but single-event upsets cause error propagation and system failure

Engineering Contradiction:
Improveradiation hardnessVSAvoidsingle-event upset effects
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements beforehand cushioning by using a watchdog mechanism that monitors calibration values and resets them when they exceed predetermined thresholds. This protective measure is prepared in advance to prevent error propagation from single-event upsets, thereby maintaining reliability in radiation conditions without requiring complex error correction codes or redundant systems.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The calibration system incorporates feedback through the watchdog mechanism that continuously monitors calibration register values and compares them against threshold limits. When radiation-induced errors cause values to exceed thresholds, the feedback loop triggers a reset, preventing system failure and maintaining reliable operation in harsh radiation environments.

Inventive Principle:
Principle #23Feedback

3Productivity

If high sampling frequencies and resolution are demanded, then ADC performance meets modern applications, but circuit complexity and cost increase significantly

Engineering Contradiction:
Improvesampling frequencyVSAvoidcircuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a universal calibration approach that works across multiple sampling frequencies and resolution levels without requiring frequency-specific or resolution-specific circuit modifications. The three-point calibration method with watchdog protection provides a single, adaptable solution that maintains high productivity across GHz-range sampling frequencies while avoiding the need for complex frequency-multiplexed calibration circuits.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Measurement precision

If calibration step size is reduced to 50 fs, then phase calibration precision improves, but calibration stability deteriorates under radiation conditions

Engineering Contradiction:
Improvephase calibration precisionVSAvoidcalibration stability
Core Design Contradiction:
Measurement precisionVSStability of the object's composition

Solution Approach 1:

The watchdog mechanism provides beforehand cushioning by establishing predetermined threshold limits for calibration values before radiation events occur. These thresholds are set to accommodate the fine 50 fs calibration steps while preventing instability from radiation-induced errors, thereby maintaining both precision and stability through pre-configured protective boundaries.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentEP3211796B1Radiation-hardened interleaved analog-to-digital converter circuits and methods of calibrating the same
Publication Date: 2019.04.10 THE BOEING CO
  • EP3211796B1 patent drawingFigure 1
  • EP3211796B1 patent drawingFigure 2
  • EP3211796B1 patent drawingFigure 3

AI summary

An analog-to-digital converter (ADC) includes at least first thru third ADC slices configured to sample input signal and transmit first thru third digitally converted values thereof, at least one reference ADC slice configured to sample input signal and transmit a digitally converted reference value, first thru third and reference registers coupled to first thru third and reference ADC slices, respectively, a delay register having an input and output, and configured to produce a sample time adjustment signal, where the sample time adjustment signal facilitates adjustment of a phase of a next time sampling of the input signal by the second ADC slice, and a plurality of computational circuit elements coupled to the input, output, and the registers, and configured to determine values of an error, an approximate time derivative of the input signal estimated from the third, second and first sampled time point, and the sample time adjustment signal.