Radiation-Hardened CMOS Logic Device Using Shared Transistor Nodes
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Solution Overview
Problem
Existing radiation-hardened solutions for combinational logic cells are unsatisfactory as they either introduce new logic cells that can cause single event transients (SETs) or incur performance penalties due to capacitive load and temporal filtering.
Innovation Solution
A radiation-hardened logic device is designed with n-channel and p-channel transistors coupled between the output node and supply/ground voltage rails, sharing common source/drain regions and having gates connected to the output node, with optional delay elements to manage radiation-induced voltage transients without creating additional output nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If radiation-hardening solutions are implemented for combinational logic cells, then reliability against radiation-induced errors is improved, but device complexity increases due to addition of new logic cells
Solution Approach 1:
The radiation-hardening circuit is merged with the existing logic device by sharing the same output node and using the existing transistor structure. The first n-channel transistor and first p-channel transistor are integrated into the logic device such that they share common source/drain regions with other transistors in the logic device, eliminating the need for separate radiation-hardening logic cells.
Solution Approach 2:
The first n-channel transistor and first p-channel transistor serve dual functions: they are part of the logic device's normal operation and simultaneously provide radiation-hardening protection. These transistors function both as regular logic transistors and as protection transistors that collect radiation-induced carriers, eliminating the need for dedicated protection circuits.
2Reliability
If additional transistors are added for radiation hardening, then protection against single event transients is improved, but manufacturing precision requirements increase
Solution Approach 1:
The radiation-hardening transistors are manufactured using the same fabrication process as the logic device transistors. The first n-channel transistor is formed in a p-type well and shares common source/drain regions with other n-channel transistors in the logic device. The first p-channel transistor is formed in an n-type well and shares common source/drain regions with other p-channel transistors, ensuring identical manufacturing conditions and precision requirements.
3Reliability
If radiation-hardening circuits are added to combinational logic, then reliability is improved, but performance penalty increases due to capacitive load
Solution Approach 1:
The radiation-hardening transistors share the same output node as the logic device, eliminating additional capacitive load that would arise from separate protection circuits. The first n-channel transistor and first p-channel transistor are coupled by their main conducting nodes between the output node and supply voltage rails, integrating their capacitance into the existing logic device output capacitance.
Data Source
AI summary
A radiation-hardened logic device includes a first n-channel transistor coupled by its main conducting nodes between an output node of a logic device and a supply voltage rail and a first p-channel transistor coupled by its main conducting nodes between the output node of the logic device and a ground voltage rail. The gates of the first n-channel and p-channel transistors are coupled to the output node.