Radiation Hardened Latch Using Cross-Connected Complementary Outputs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS circuits in space applications are vulnerable to single event upsets (SEUs) due to radiation exposure, particularly at high frequencies where the timing window for set and hold of flip flops is consistently covered by SEU hits, leading to potential soft errors.
Innovation Solution
A radiation hardened programmable phase frequency divider design utilizing dual master and slave latch circuits with complementary data inputs and outputs, implemented in deep submicron CMOS technology, which connects clock inputs and data inputs in parallel and cross-connects data outputs as feedback inputs to mitigate the effects of SEUs, ensuring operation immunity to single event upsets at GHz frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual interlocked cell (DICE) type flip flop design is used to protect against SEU hits, then reliability is improved for low frequency operation, but the timing window vulnerability remains covered at high frequencies (GHz range)
Solution Approach 1:
The flip-flop is divided into two identical half circuits with separate but parallel data input paths. Each half circuit processes one pair of complementary data inputs independently, and the outputs are cross-connected to provide mutual validation. This segmentation allows the circuit to maintain radiation hardness while operating at high frequencies by distributing the critical path across parallel independent paths.
Solution Approach 2:
Two identical half circuits are merged into a single flip-flop structure with cross-connected outputs. The combined structure uses the outputs of one half circuit to validate the outputs of the other half circuit, creating a unified radiation-hardened flip-flop that operates at high frequencies. The merging of parallel paths provides both speed and reliability.
2Speed
If the vulnerable timing window for set and hold is reduced to enable GHz operation, then speed is improved, but the circuit becomes more susceptible to SEU hits covering the entire timing window
Solution Approach 1:
The outputs of each half circuit are cross-connected to the feedback inputs of the other half circuit, creating a mutual validation mechanism. This feedback allows each half circuit to monitor and validate the state changes of the other, ensuring that single event upsets cannot cause incorrect state transitions even at high frequencies where the timing window is continuously vulnerable.
Solution Approach 2:
Two identical copies of the half circuit are used with cross-connected outputs. Each copy serves as a redundant validation of the other, and the copying approach ensures that a single event upset affecting one copy cannot corrupt the overall flip-flop state. This copying strategy maintains radiation hardness while enabling high-speed operation.
3Reliability
If dual complementary data inputs are used in each half circuit, then reliability against SEU is improved, but device complexity increases
Solution Approach 1:
Each half circuit is designed with specific local characteristics (complementary data input pairs) that provide radiation hardness at the local level. The local quality of each half circuit is optimized for SEU immunity, and the cross-connection of outputs extends this protection to the overall flip-flop structure without requiring complex global redesign.
Solution Approach 2:
While the two half circuits are identical in structure, their interconnection creates an asymmetric validation relationship where each half circuit's outputs validate the other's state changes. This asymmetric cross-validation approach provides radiation hardness with relatively simple circuitry, avoiding the need for more complex symmetric redundancy schemes.
Data Source
AI summary
A programmable phase frequency divider for space applications is implemented in CMOS technology, and consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU's. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit. Therefore, a radiation hardened programmable phase frequency divider that is immune to SEU's is achieved.