Radiation-Hardened Logic Cell Layout for Multiple-Node Soft Errors
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Solution Overview
Problem
Current technologies face challenges in effectively protecting logic circuits against multiple node soft errors, which are exacerbated in ultra-deep submicron technologies due to increased sensitivity to radiation-generated soft-errors, and existing methods like triplication and duplication result in undesirable power and area overhead, failing to handle multiple bit upsets and single-event multiple upsets efficiently.
Innovation Solution
A unique layout method that arranges critical contact areas to oppose single event pulses, ensuring that errors are canceled or greatly reduced, and uses primary and secondary circuits with specific rules to maintain error-free operation, applying to both sequential and combinational logic elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triplication or duplication methods are used to protect against single event errors, then reliability is improved, but power consumption and area increase
Solution Approach 1:
The patent combines the protection function into the standard cell layout itself rather than using separate redundant circuits. The critical contact areas are positioned to naturally cancel single event pulses through their spatial arrangement, eliminating the need for separate triplication or duplication circuits and their associated voting logic, thereby reducing power consumption while maintaining reliability
2Reliability
If triplication or duplication methods are used to protect against single event errors, then reliability is improved, but area increases
Solution Approach 1:
The protection mechanism is merged into the standard cell layout by strategically positioning critical contact areas within the existing cell structure. This approach provides multiple node error protection without requiring additional redundant cells, voting circuits, or filtering logic, thereby maintaining compact cell area while achieving reliability improvement
3Ease of manufacture
If standard commercial semiconductor manufacturing is used, then manufacturing cost is reduced, but radiation tolerance decreases
Solution Approach 1:
The patent applies local quality by modifying only the critical contact area positions within the cell layout while maintaining compatibility with standard manufacturing processes. The specific spatial arrangement of contact areas provides radiation hardness against multiple node errors without requiring changes to the overall manufacturing process, thus maintaining ease of manufacture while improving resistance to radiation effects
4Productivity
If feature size is reduced to increase integration, then productivity is improved, but sensitivity to soft errors increases
Solution Approach 1:
The patent addresses the sensitivity issue by applying local quality to the critical contact areas within the high-density integrated circuit. The specific positioning of contact areas creates a layout that is inherently resistant to multiple node errors even at reduced feature sizes, allowing high integration levels to be maintained while mitigating the increased soft error sensitivity that would otherwise result from smaller dimensions
Data Source
AI summary
This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modern technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.