Radiation-Hardened Memory Scrub Circuit With Redundant EDAC
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Solution Overview
Problem
CMOS integrated circuits operating in extreme environments are prone to increased failure rates due to radiation exposure, leading to unreliable operation and potential system failures, as they are sensitive to single event effects such as soft errors, latch-up, and ionizing radiation-induced degradation.
Innovation Solution
The integration of spatially redundant circuitry, buried guard ring (BGR) structures, and parasitic isolation device (PID) structures into CMOS circuits, along with error detection and correction (EDAC) and scrub circuits, enhances radiation hardening by reducing parasitic effects and improving error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spatially redundant circuitry and error correction circuits are added to CMOS circuits, then reliability is improved, but device complexity increases
Solution Approach 1:
The memory array is divided into multiple banks, with each bank having its own dedicated scrub circuit and EDAC circuit. This segmentation allows parallel error correction operations across different memory regions, improving reliability through redundancy while managing complexity by localizing correction functions to specific segments rather than requiring a single complex global correction system.
Solution Approach 2:
The scrub circuits continuously and autonomously scan memory banks to detect and correct errors before they affect system operation. This preliminary action prevents error accumulation and maintains reliability proactively, rather than waiting for errors to manifest as system failures, thereby reducing the need for more complex reactive error handling mechanisms.
2Reliability
If scrub circuits continuously scan memory to correct errors, then reliability is improved, but use of energy increases
Solution Approach 1:
The scrub circuits operate by periodically scanning through memory banks in sequence, correcting errors in each bank before moving to the next. This periodic operation allows the system to maintain high reliability through continuous error correction while managing power consumption by keeping scrub circuits inactive during normal memory operations and activating them only during scheduled scrub cycles.
Solution Approach 2:
The scrub circuits are designed to autonomously scan, detect, and correct errors without requiring external control signals or intervention. This self-service capability allows the memory system to maintain its own reliability independently, reducing the power overhead associated with external error management hardware or software.
3Productivity
If multiple scrub circuits are used to scan multiple memory banks, then productivity is improved, but device complexity increases
Solution Approach 1:
The memory system is divided into multiple independent banks, each with its own scrub circuit. This segmentation enables parallel error correction operations across different memory regions, significantly improving the overall throughput and productivity of the error correction system. Each scrub circuit operates independently on its assigned bank, allowing simultaneous error correction in multiple banks without interference.
Solution Approach 2:
Each scrub circuit is designed with a universal architecture that can scan and correct errors in its assigned memory bank using the same operational sequence. This multi-functionality allows identical scrub circuit designs to be replicated across multiple banks, simplifying the overall system design while achieving high error correction throughput through parallel operation of multiple identical units.
Data Source
AI summary
An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.