Radio-Frequency Front-End Trigger Timing on One-Wire Buses

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Solution Overview

Problem

The increasing complexity of mobile communication devices demands improved timing management techniques for serial bus communication, particularly when a clock signal is not transmitted over a dedicated wire, especially in systems with one-wire and two-wire subordinate devices sharing a common data line, to minimize frequency mismatches and enhance communication efficiency.

Innovation Solution

A receiving device generates a base clock signal, counts cycles or edges using a counter, and adjusts the count value with a correction factor to synchronize trigger actuation, utilizing a locally-generated clock signal to manage timing for one-wire and two-wire subordinate devices on a shared serial bus.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single-wire serial bus is used to reduce GPIO pins, then device complexity is reduced, but timing precision deteriorates due to lack of dedicated clock signal

Engineering Contradiction:
Improvebus architecture complexityVSAvoidtrigger timing precision
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

A correction value acts as an intermediary between the imprecise locally-generated clock and the required precise trigger timing. The correction value compensates for frequency mismatches, enabling accurate trigger actuation despite using a single-wire bus without dedicated clock signal.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system changes the timing parameter dynamically by applying a correction value that adjusts for frequency deviations. This allows the trigger timing to be precisely controlled even when the locally-generated clock frequency differs from the transmitter clock frequency.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If locally-generated clock signal is used for timing, then device complexity is reduced, but frequency mismatch increases causing timing errors

Engineering Contradiction:
Improveclock signal generationVSAvoidtrigger timing accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The system measures the actual duration of a reference pulse using the locally-generated clock and compares it to the expected duration. Based on this feedback, a correction value is calculated and applied to subsequent trigger timing operations, continuously compensating for frequency mismatches.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The correction value is pre-calculated during an initialization phase by measuring a reference pulse. This preliminary measurement allows the system to compensate for frequency mismatches in all subsequent trigger operations without requiring continuous calibration.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If correction value is applied to compensate frequency mismatch, then trigger timing precision is improved, but device complexity increases

Engineering Contradiction:
Improvetrigger timing precisionVSAvoidtiming management complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Each receiving device independently calculates and applies its own correction value based on its locally-generated clock characteristics. This self-service approach eliminates the need for complex centralized timing management while achieving precise trigger timing across multiple devices.

Inventive Principle:
Principle #25Self-service

4Device complexity

If multiple subordinate devices share common data line, then bus architecture is simplified, but communication efficiency deteriorates due to timing synchronization issues

Engineering Contradiction:
Improvebus architectureVSAvoidcommunication efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The correction value mechanism serves multiple functions: it compensates for frequency mismatches, synchronizes trigger timing across different devices with different local clock frequencies, and enables reliable communication on the shared bus. This universal solution improves communication efficiency without requiring separate clock lines for each device.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12443217B2Time actuated triggers for a radio frequency front end
Publication Date: 2025.10.14 QUALCOMM INC
  • US12443217B2 patent drawing
  • US12443217B2 patent drawing
  • US12443217B2 patent drawing

AI summary

A receiving device, comprising: a clock generator circuit configured to generate a base clock signal; a counter configured to count cycles or edges of the base clock signal while a measurement pulse is received over a one-wire serial bus during a first transaction conducted over the one-wire serial bus, the measurement pulse having a pulse duration defined by a number of clock cycles of a transmitter clock signal; and a controller configured to adjust a count value of the counter when the counter is timing actuation of a trigger using a correction value that represents a difference between the cycles or edges of the base clock signal counted while the measurement pulse was being received and the number of clock cycles of the transmitter clock signal that defines the pulse duration.