Switched-Capacitor Radio Receiver for Low-Noise 65 nm Operation
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Solution Overview
Problem
Designing radio receivers using conventional architectures in integrated circuit fabrication technologies with feature sizes of 65 nm and less is challenging due to limited dynamic range, low intrinsic voltage gain, high flicker noise, and difficulties in cascoding transistors, primarily because of headroom issues and the squirrely behavior of field effect transistors (FETs).
Innovation Solution
A radio receiver architecture that includes an antenna, a first mixer, a buffer, and multiple charge pumps, with switched-capacitor charge pumps and chopper stabilization circuits, which provide improved signal processing and noise reduction by increasing voltage gain and reducing noise figure, thereby overcoming the limitations of small feature size transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional radio receiver architectures are used in 65 nm and less fabrication technologies, then device complexity is reduced, but dynamic range is limited and noise figure deteriorates
Solution Approach 1:
The radio receiver architecture is segmented into multiple functional blocks: antenna, first mixer, buffer, first charge pump, second charge pump, chopper stabilization circuit, and second mixer. Each block performs a specific function in the signal processing chain, allowing the system to achieve high dynamic range through coordinated operation of specialized sub-components rather than relying on a single complex amplifier stage.
Solution Approach 2:
A buffer is introduced as an intermediary component between the first mixer and the charge pumps. This buffer provides impedance matching and signal level conditioning, enabling better transfer of the mixed signal to subsequent stages while maintaining signal integrity and reducing noise figure without requiring the preceding mixer stage to directly drive the high-impedance charge pump inputs.
2Manufacturing precision
If conventional architectures are used, then manufacturing is simpler, but intrinsic voltage gain from transistors is low and flicker noise is high
Solution Approach 1:
The patent replaces traditional voltage amplification mechanisms (relying on high-gain transistor stages) with charge-based signal processing using switched-capacitor charge pumps. This substitution allows the system to achieve high effective gain through charge accumulation and transfer rather than relying on the intrinsic voltage gain of small-feature-size transistors, thereby overcoming the limitations of 65 nm and less fabrication processes.
Solution Approach 2:
The invention changes the fundamental operating parameters of the signal processing stages by using charge pumps that operate at different phases and frequencies. The first charge pump operates at a first frequency while the second charge pump operates at a second frequency, allowing the system to achieve high gain and low noise figure through parameter diversity rather than relying on single high-performance transistor parameters.
3Area of stationary object
If small feature size transistors are used, then integration density is improved, but headroom issues prevent cascoding and FET behavior becomes unpredictable
Solution Approach 1:
The patent employs periodic switching action in the charge pumps, where capacitors are periodically charged during a first time interval and then connected in series during a second time interval. This periodic operation allows the system to build up high voltage gain through repeated charge transfer cycles, compensating for the low intrinsic gain of small-feature-size transistors without requiring cascoded transistor structures that would consume excessive headroom.
Solution Approach 2:
The invention introduces dynamic reconfiguration of the charge pump circuits, where the connection topology of capacitors changes periodically between parallel (during charging) and series (during output) configurations. This dynamic operation enables the system to achieve high effective gain and adapt to varying signal conditions, overcoming the static limitations and unpredictable behavior of small-feature-size FETs in conventional fixed-topology circuits.
4Reliability
If multiple charge pumps and mixers are added, then noise figure is reduced and dynamic range is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple charge pump stages and mixer stages into an integrated signal processing chain where the first mixer feeds into the first charge pump, which feeds into the second charge pump, which feeds into the second mixer. This merging of multiple functional blocks into a unified architecture allows the system to achieve low noise figure and high dynamic range through the cumulative effect of each stage while sharing common biasing and control infrastructure, thereby managing overall complexity.
Data Source
AI summary
A baseband signal-conditioning architecture applicable to radio receivers uses switched-capacitor techniques to provide high-performance signal conditioning in low-voltage, deep-submicron processes (e.g., 65 nm and below). In the architecture, a first mixer is coupled to an antenna receiving the signal, and outputs a first mixer output signal based on the signal received by the antenna. A buffer coupled to an output of the first mixer outputs a buffer signal based on the first mixer output signal. A first charge pump is coupled to an output of the buffer, and produces a first charge pump output signal based on the buffer signal. In some examples, a second charge pump is coupled to the output of the first mixer and produces a second charge pump output signal based on the first mixer output signal, and the buffer input is coupled to an output of the second charge pump.