Radio Receiver Timing Using Dual Clocks and Gated Buffering
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Solution Overview
Problem
Conventional radio receivers in cellular networks, particularly in LTE systems, face challenges with timing precision due to asynchronous analogue-to-digital converter sample rates, leading to power inefficiencies and signal demodulation issues, especially in low-power applications like battery-operated devices.
Innovation Solution
A radio receiver device with an analogue circuit portion and a digital circuit portion, where the digital processing units are clocked by a second clock derived from the ADC clock, and a network timer ensures accurate synchronization using a higher frequency network clock, allowing for improved timing precision without needing to synchronize the internal time base with the network time base, thus reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the analogue-to-digital converter is clocked at a lower frequency to reduce power consumption, then power efficiency improves, but timing precision deteriorates
Solution Approach 1:
The patent combines two clock domains: a low-frequency ADC clock for power efficiency and a high-frequency network timer clock for timing precision. The network timer generates receive enable flags that are resynchronized to the ADC clock domain, merging the benefits of both frequency domains into a unified reception system.
Solution Approach 2:
The network timer acts as an intermediary between the high-precision network timing and the low-power ADC operation. It generates receive enable flags based on network timing that are then resynchronized to the ADC clock, mediating between the two conflicting requirements.
2Measurement precision
If the receiver synchronizes its internal time base with the network time base, then timing alignment improves, but power consumption increases due to higher clock frequencies
Solution Approach 1:
The patent segments the timing function into two parts: network timing for synchronization decisions (handled by the network timer) and ADC sampling timing (handled by the ADC clock). This allows the ADC to operate at low power while still achieving network synchronization through the resynchronized receive enable flags.
Solution Approach 2:
The patent changes the clock frequency parameter of the ADC from a high frequency (that would synchronize with network timing) to a low frequency for power efficiency, while compensating for this change by using network timer-generated enable flags that are resynchronized to the new clock domain.
3Reliability
If digital filtering is applied to remove transients from the output data stream, then signal quality improves, but processing resources and power are wasted
Solution Approach 1:
The patent performs preliminary action by using the network timer to predict exactly when valid data will arrive and generates receive enable flags in advance. This allows the buffer to be enabled only when needed, avoiding the waste of processing and storing transient data that would require filtering to remove.
4Reliability
If the receiver enables the buffer continuously to capture all incoming data, then no data is lost, but power is wasted processing invalid transient data
Solution Approach 1:
The system uses feedback from the network timer about when valid data frames are expected to arrive. This feedback controls the buffer enable signal, ensuring the buffer is active only during valid data reception windows and inactive during transient periods, achieving both complete data capture and power efficiency.
Data Source
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AI summary
A radio receiver device(1), arranged to receive a radio signal (38) modulated with a plurality of data symbols, comprises an analogue-to-digital converter (32) that is clocked by a first clock signal (54) and is arranged to receive the radio signal and produce a digital signal (56, 58). A digital circuit portion (6), arranged to receive the digital signal produced by the analogue-to-digital converter, comprises digital processing units (62a-c, 64a-c) that are clocked by a second clock (84) derived from the first clock and arranged to process the digital signal and produce an output signal (90, 92) at an output sample rate. A counter (72), clocked by the second clock,counts a number of samples at the output sample rate. A network timer (74) clocked by a reference of a network clock (76) produces a receiver enable flag (78) which is synchronised (70) to the first clock. The counter is enabled only when the synchronised flag (80) is set. The counter is arranged to set a trigger flag (98) when the number of samples exceeds a predetermined threshold. A buffer (100) is arranged to receive the output signal and is enabled only when the trigger flag is set.