Radix-3 Butterfly Instruction for Lower-Latency DFT Computation
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Solution Overview
Problem
Increasing processing resources in portable electronic devices, such as through more powerful processor cores or multiple cores, leads to increased cost and power consumption, impacting user satisfaction.
Innovation Solution
A single instruction, such as the 'AddSubD2' instruction, is used to perform radix-3 butterfly computations by combining the results of three smaller DFTs, reducing the number of processor cycles required and improving computational efficiency without increasing cost or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more powerful processor cores or multiple processor cores are used to improve computational efficiency, then processing capability is improved, but cost and power consumption increase
Solution Approach 1:
The patent combines multiple operations (addition, subtraction, and division by 2) into a single processor instruction. This merging of operations reduces the total number of instructions executed, thereby improving computational efficiency without requiring additional processor cores or increased processing power, thus avoiding increased power consumption.
Solution Approach 2:
The patent optimizes the computational parameters by using division by 2 (which can be implemented as a simple bit shift operation) rather than general division. This parameter change allows the processor to perform the operation more efficiently using existing hardware capabilities, improving productivity without increasing power consumption.
2Productivity
If more powerful processor cores or multiple processor cores are used to improve computational efficiency, then processing capability is improved, but device cost increases
Solution Approach 1:
The patent combines multiple operations (addition, subtraction, and division by 2) into a single processor instruction. This merging of operations reduces the total number of instructions executed, thereby improving computational efficiency without requiring additional processor cores or increased processing power, thus avoiding increased device cost.
Solution Approach 2:
The patent utilizes the processor's existing arithmetic logic unit and register file to perform the combined operations. The processor serves itself by using its own existing resources efficiently, rather than requiring additional hardware components, thereby improving productivity without increasing manufacturing cost.
3Measurement precision
If traditional multi-instruction approaches are used for radix-3 butterfly computations, then computational accuracy is maintained, but the number of processor cycles and latency increase
Solution Approach 1:
The patent combines multiple operations (addition, subtraction, and division by 2) into a single processor instruction. By executing these operations atomically in one instruction cycle, the patent reduces latency and the number of processor cycles required, while maintaining computational accuracy through precise handling of intermediate results within the processor's arithmetic logic unit.
Data Source
AI summary
A device includes a processor and a memory configured to store instructions. The processor is configured to receive a particular instruction from among the instructions and to execute the particular instruction to generate first output data corresponding to a sum of first input data and second input data. The processor is also configured to execute the particular instruction to perform a divide operation on the second input data and to generate second output data corresponding to a difference of the first input data and a result of the divide operation.