Radix-4 Multiplier Circuit With Tripler Partial Product Generation
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Solution Overview
Problem
Multiplier circuits in integrated circuits, particularly in AI applications, consume significant area and energy resources due to the large number of instances required, and existing decoding schemes for partial product generation are complex and inefficient.
Innovation Solution
The use of direct radix 4 decoding and tripler circuitry with decomposed carry prefix trees in multiplier circuits to generate partial products, reducing complexity and resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional decoding schemes are used for partial product generation, then multiplication functionality is achieved, but circuit complexity and resource consumption increase significantly
Solution Approach 1:
The patent segments the multiplier bits into groups of two (d0, d1), (d2, d3), etc., and applies direct radix-4 decoding to each group independently. This segmentation reduces the decoding complexity from O(n) for traditional schemes to O(n/2) for radix-4, while maintaining complete multiplication functionality through systematic processing of all bit groups.
Solution Approach 2:
The patent changes the numerical base parameter from binary (base-2) to radix-4 (base-4) in the decoding scheme. This parameter change allows two binary bits to be decoded simultaneously as a single radix-4 digit, reducing the number of decoding operations by half and thereby reducing circuit complexity while preserving multiplication accuracy.
2Productivity
If more multiplier instances are implemented for AI applications, then computational capability increases, but area and energy consumption increase significantly
Solution Approach 1:
The patent implements partial product generation only where strictly necessary by using direct radix-4 decoding that processes two bits at a time. This partial action approach generates exactly the required number of partial products without excessive computation, reducing the area and energy overhead while maintaining the computational capability needed for AI applications.
3Productivity
If more multiplier instances are implemented for AI applications, then computational capability increases, but energy consumption increases significantly
Solution Approach 1:
By segmenting the multiplication into radix-4 groups, the patent reduces the total number of partial product generations required. Each radix-4 decoding group processes two bits simultaneously, reducing the overall operation count and thereby reducing energy consumption while maintaining computational capability for AI workloads.
Solution Approach 2:
Changing from binary to radix-4 parameterization reduces the number of logical operations required per multiplication by approximately half. This parameter change directly translates to reduced switching activity and lower dynamic power consumption, making the multiplier more energy-efficient for AI applications.
Data Source
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AI summary
Integrated circuit devices, methods, and circuitry for an efficient multiplier are provided. Multiplier circuitry to multiply a multiplicand value with a multiplier value may include, among other things, decoding circuitry, tripler circuitry, and partial product multiplexing circuitry. The decoding circuitry may decode bits of the multiplier value using a decoding scheme that includes at least a coding that indicates a triple, the tripler circuitry may generate a triple of the multiplicand value and may include circuitry to generate the triple of the multiplicand value that sums at least two different vectors, and the partial product multiplexing circuitry may select the triple of the multiplicand as a partial product when the coding indicates the triple.