Hardware RAID Acceleration via Command Coalescing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The PCIe bus in current information handling systems experiences duplication of upstream and downstream transactions, leading to increased data transmission times and latency due to concurrent access across multiple endpoints, which reduces bandwidth capacity and increases system latency.
Innovation Solution
A hardware logic device is introduced to receive I/O commands from the host system processor, store them in a controller memory, communicate notifications to memory storage devices, coalesce command fetch requests, and duplicate command fetch responses, thereby optimizing data transmission and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PCIe endpoints access the same physical memory address concurrently, then device connectivity and functionality are improved, but transaction duplication occurs increasing latency and reducing bandwidth capacity
Solution Approach 1:
The patent introduces a memory controller as an intermediary component between PCIe endpoints and system memory. This controller consolidates multiple concurrent access requests into a single coordinated transaction, eliminating duplication while maintaining connectivity benefits. The memory controller manages the arbitration and coordination of multiple endpoints accessing the same memory address, resolving the contradiction between connectivity and transmission time.
Solution Approach 2:
The patent merges multiple concurrent PCIe transactions into a single coordinated memory access operation. By combining duplicate read/write requests from multiple endpoints into one unified transaction handled by the memory controller, the system maintains the functionality of multiple devices while eliminating redundant data transmissions, thereby reducing latency and improving bandwidth efficiency.
2Adaptability or versatility
If multiple PCIe endpoints access the same physical memory address concurrently, then device connectivity and functionality are improved, but bandwidth capacity is reduced due to transaction duplication
Solution Approach 1:
The memory controller serves as a mediator that coordinates access from multiple PCIe endpoints, ensuring that concurrent requests are handled efficiently without duplicating transactions. This intermediary manages the arbitration process and ensures that each unique memory access is performed only once, thereby maintaining high bandwidth capacity while supporting multiple connected devices.
Solution Approach 2:
The patent combines multiple concurrent access transactions into a single coordinated operation handled by the memory controller. This merging of transactions eliminates redundant data transmissions, ensuring that the full PCIe bandwidth capacity is available for actual data transfers rather than being consumed by duplicate requests from multiple endpoints.
3Productivity
If a hardware logic device emulates controller memory and coalesces commands, then data transmission efficiency is improved, but device complexity increases
Solution Approach 1:
The patent employs a hardware logic device that creates a virtual copy or emulation of the controller memory interface. This emulated controller memory allows the system to intercept and coalesce commands from multiple PCIe endpoints without requiring physical changes to the original memory architecture. The copying approach enables command consolidation while maintaining compatibility with existing systems, managing complexity through virtualization rather than hardware redesign.
Data Source
AI summary
In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a host system processor of the information handling system, an input/output (I/O) command; storing the I/O command in a controller memory of the hardware logic device that emulates to the host system processor a controller memory of a memory storage device; communicating a notification of the I/O command to a plurality of memory storage devices communicatively coupled to the hardware logic device; coalescing a plurality of command fetch requests received from individual memory storage devices of the plurality of memory storage devices into a coalesced command fetch request; communicating the coalesced command fetch request to the controller memory; and duplicating a command fetch response from the controller memory of the coalesced command fetch request to the plurality of memory storage devices.