Simplified RAID for Byte-Addressable Memory via Media Controllers
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Solution Overview
Problem
Conventional RAID technologies are not suitable for byte-addressable memory devices due to prolonged transaction-processing times and complex hardware logics required for implementation.
Innovation Solution
A simplified implementation of RAID for byte-addressable memory devices, where each media controller maintains a RAID-group-mapping table and cooperatively provides RAID functionality at a granularity level suitable for byte-addressable memory, such as at the cache-line level, using an exclusive OR (XOR) checksum scheme.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RAID technologies are implemented on byte-addressable memory devices, then data redundancy and reliability are improved, but transaction-processing time increases and hardware logic complexity increases
Solution Approach 1:
The patent segments the RAID implementation into independent media controller units, each capable of autonomous RAID operations. By dividing the system into multiple independent controllers that can operate in parallel, the patent reduces transaction-processing time while maintaining data redundancy through distributed RAID group management across the segmented controllers.
Solution Approach 2:
The patent implements preliminary action by pre-calculating and storing RAID group mapping information in lookup tables within each media controller. This allows controllers to quickly determine stripe assignments and parity calculations without complex real-time computations, thereby reducing transaction-processing time while preserving reliability through pre-established redundancy schemes.
2Reliability
If conventional RAID technologies are implemented on byte-addressable memory devices, then data redundancy and reliability are improved, but hardware logic complexity increases
Solution Approach 1:
The patent extracts the complex RAID logic from the byte-addressable memory devices and relocates it to dedicated media controllers. Each media controller contains simplified logic for managing RAID groups, while the memory devices themselves remain simple storage units. This extraction reduces hardware logic complexity at the memory device level while maintaining data redundancy through the distributed controller architecture.
Solution Approach 2:
The patent introduces media controllers as intermediary components between the host system and byte-addressable memory devices. These controllers handle all complex RAID operations including parity calculation, stripe management, and redundancy maintenance, thereby reducing the hardware logic complexity required in the memory devices themselves while preserving full RAID functionality through the intermediary controllers.
3Adaptability or versatility
If RAID functionality is provided at byte-addressable granularity, then adaptability to memory systems is improved, but hardware logic complexity and transaction-processing time increase
Solution Approach 1:
The patent implements universal media controllers that can handle multiple RAID levels and configurations through a unified architecture. Each controller is designed to be multi-functional, supporting various byte-addressable memory device types and RAID configurations without requiring device-specific complex logic. This universality improves adaptability to different memory systems while reducing hardware logic complexity through standardized multi-purpose controller design.
Data Source
AI summary
One aspect of the instant application can provide a storage system. The storage system can include a plurality of byte-addressable storage devices and a plurality of media controllers. A respective byte-addressable storage device is to store a parity block or a data block of a data stripe, and a respective media controller is coupled to a corresponding byte-addressable storage device. Each media controller can include a tracker logic block to serialize critical sections of multiple media-access sequences associated with an address on the corresponding byte-addressable storage device. Each media-access sequence comprises one or more read and/or write operations, and the data stripe may be inconsistent during a critical section of a media-access sequence.


