RAID Memory Controller Erase Synchronization

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Solution Overview

Problem

Current memory systems face inefficiencies in data access and power management, particularly in RAID configurations, where simultaneous data retrieval and refresh operations can lead to increased power consumption and latency, and existing solutions do not effectively coordinate erase operations across memory modules.

Innovation Solution

A memory system with a memory controller that coordinates erase operations across a RAID group, allowing only one module to perform erase operations at a time, and independently scheduling refresh operations to minimize latency and power usage, while enabling simultaneous data retrieval from multiple modules.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple memory modules perform erase operations simultaneously in a RAID group, then the total erase capacity increases, but power consumption increases and data integrity cannot be guaranteed

Engineering Contradiction:
Improveerase operation throughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic, sequential erase operations across memory modules in a RAID group. The memory controller coordinates erase operations to occur in time intervals rather than simultaneously, with each module taking turns to perform erases while others remain idle or perform reads. This periodic scheduling reduces peak power consumption while maintaining acceptable erase throughput for the RAID group.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent segments the erase operation workload across multiple time intervals and memory modules. Instead of all modules erasing simultaneously, the erase operation is divided into sequential phases where different modules perform erases at different times. This segmentation allows the system to achieve total erase capacity over time while limiting instantaneous power consumption to safe levels.

Inventive Principle:
Principle #1Segmentation

2Loss of time

If memory modules perform erase operations simultaneously, then the erase operations complete faster, but the complexity of coordinating and managing these operations increases

Engineering Contradiction:
Improvetotal erase timeVSAvoidcoordination complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent introduces a memory controller as an intermediary that manages and coordinates erase operations across multiple memory modules. The controller acts as a central authority that schedules, initiates, and monitors erase operations, simplifying the coordination complexity by centralizing control rather than requiring complex peer-to-peer coordination between modules. This intermediary approach makes the system more manageable despite the sequential nature of operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Duration of action of stationary object

If refresh operations are performed while data is being retrieved from memory modules, then refresh completion time is reduced, but power consumption increases

Engineering Contradiction:
Improverefresh operation durationVSAvoidpower consumption
Core Design Contradiction:
Duration of action of stationary objectVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic scheduling of refresh operations separate from data retrieval operations. The memory controller coordinates refresh cycles to occur in dedicated time intervals when data retrieval is minimized or paused. This periodic separation allows refresh operations to complete more quickly without the added power consumption of simultaneous read operations, as the system can enter lower-power states during refresh-only periods.

Inventive Principle:
Principle #19Periodic action

4Use of energy by moving object

If erase operations are coordinated sequentially across memory modules, then power consumption is reduced, but the total time to complete all erase operations increases

Engineering Contradiction:
Improvepower consumptionVSAvoidtotal erase time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent maintains continuity of useful action by ensuring that while one memory module performs erase operations, other modules in the RAID group can simultaneously perform data retrieval operations. This continuous utilization of system resources means that the sequential erase scheduling does not result in idle time for the overall system, as other modules remain productive. The total erase time increases slightly, but the system maintains high utilization through continuous useful actions in parallel.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS10176861B2RAIDed memory system management
Publication Date: 2019.01.08 INNOVATIONS IN MEMORY LLC
  • US10176861B2 patent drawing
  • US10176861B2 patent drawing
  • US10176861B2 patent drawing

AI summary

A memory system is described, where a plurality of memory modules is connected to a memory controller. Erase operations of the memory modules are coordinated by the memory controller such that, when data is stored in a group of memory modules configured to be a RAID (Redundant Array of Independent “Disks”) group, erase or refresh operations performed on the memory modules of the RAID group are synchronized, scheduled, or controlled to reduce the latency in reading the data stored on the RAID modules.