RAID Memory System with Parity for Low Latency Access
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Solution Overview
Problem
Current computer memory systems face bottlenecks in data access time due to the latency of persistent storage media, particularly in large data centers where random access to memory locations is required, and the limitations of flash memory technologies in terms of access speed and lifetime.
Innovation Solution
A memory system comprising a plurality of memory modules with error correcting codes and a parity block, where data blocks and parity data are distributed across multiple modules, allowing for efficient recovery of data even if one module fails, and write operations are sequenced to minimize conflicts with read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If data is stored in persistent storage devices like flash memory or disk, then data retention without power is achieved, but data access time latency increases significantly
Solution Approach 1:
The patent segments data storage into multiple independent memory modules organized in stripes, where each module can be accessed independently. This allows the system to retrieve data from multiple modules simultaneously, reducing overall access latency while maintaining persistent storage capabilities across the distributed modules.
Solution Approach 2:
The patent implements preliminary actions by pre-computing and storing error correcting codes and parity data alongside the main data in each memory module. This allows for immediate error detection and data recovery without requiring additional processing time during read operations, thus reducing access latency while ensuring data integrity.
2Loss of time
If flash memory is used for persistent storage, then access latency is reduced compared to mechanical devices, but lifetime is limited by wear out mechanism
Solution Approach 1:
The patent applies beforehand cushioning by implementing error correcting codes and parity data that are stored in advance with the main data. These protective mechanisms cushion against data loss from wear-out failures, allowing the system to maintain reliable operation even as flash memory approaches its endurance limits through extensive read/write cycles.
Solution Approach 2:
The patent implements discarding and recovering by using error correcting codes to detect and correct bit errors that accumulate due to wear. When errors are detected, the system recovers the original data using the parity information, allowing continued use of the flash memory beyond what would normally be considered its operational lifetime.
3Manufacturing precision
If write operations are performed on memory modules, then data is updated, but read operations must wait causing performance bottleneck
Solution Approach 1:
The patent segments the memory system into multiple independently addressable modules. When a write operation is performed on one module, other modules remain accessible for read operations. This segmentation eliminates the system-wide performance bottleneck by allowing concurrent read and write operations on different modules, thereby maintaining high throughput while ensuring data update accuracy.
4Reliability
If error correcting codes and parity data are stored with main data, then data integrity is improved, but storage capacity is reduced
Solution Approach 1:
The patent applies partial action by implementing error correcting codes that can correct a limited number of bit errors rather than protecting against all possible failures. This partial protection approach provides sufficient data integrity for practical purposes while minimizing the overhead required for error correction data, thus preserving maximum storage capacity for actual user data.
Data Source
AI summary
A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.