RAID Memory Systems with Peer-to-Peer XOR Rebuilds
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In RAID-configured memory systems, data updates and rebuild operations can lead to increased load on the host, data congestion, and insufficient bus bandwidth, degrading the performance of the information processing system.
Innovation Solution
Implementing a method where the host generates exclusive-logical-OR data for multiple memory systems, which are then processed by the memory systems themselves, reducing the need for direct host involvement and optimizing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data updates or rebuild operations are performed in RAID-configured memory systems, then fault tolerance and data redundancy are maintained, but the load on the host increases and data transfer congestion occurs
Solution Approach 1:
The memory systems perform XOR operations and data processing autonomously without host intervention. When data needs to be updated or rebuilt, the controllers of the memory systems directly communicate with each other, performing calculations and data transformations independently, thus eliminating the need for the host to bear the processing load while maintaining RAID fault tolerance
Solution Approach 2:
The patent introduces an intermediary mechanism where memory system controllers directly communicate with each other for data operations. Instead of the host acting as the central coordinator for all XOR and data transfer operations, the controllers serve as intermediaries that handle these operations peer-to-peer, reducing host involvement and preventing data transfer bottlenecks
2Reliability
If data updates or rebuild operations are performed in RAID-configured memory systems, then fault tolerance and data redundancy are maintained, but data transfer congestion occurs and bus bandwidth is insufficient
Solution Approach 1:
The patent segments the data transfer path by enabling direct communication between memory system controllers. Instead of all data transfers going through the host bus, the system divides the transfer paths into direct peer-to-peer connections between controllers, segmenting the data flow to avoid congestion on any single bus while maintaining the integrity of RAID operations
Solution Approach 2:
The controllers act as intermediaries that enable direct data exchange between memory systems. This intermediary mechanism allows data to be transferred directly between controllers without bottlenecking through the host bus, thereby maintaining fast data transfer speeds while still performing the necessary XOR operations for fault tolerance
Data Source
Figure 1
Figure 2
Figure 3
AI summary
According to one embodiment, an information processing system comprises: a host (2); and a plurality of memory systems (3) each including a controller (7) and a nonvolatile memory (5), the plurality of memory systems (3) including at least a first memory system, a second memory system, and a third memory system, wherein the controller (7) of the first memory system is configured to store first data in a first nonvolatile memory (5) that is the nonvolatile memory (5) of the first memory system, the controller (7) of the second memory system is configured to store second data in a second nonvolatile memory (5) that is the nonvolatile memory (5) of the second memory system, the controller (7) of the third memory system is configured to store a parity in a third nonvolatile memory (5) that is the nonvolatile memory (5) of the third memory system, the first data, the second data, and the parity constitute at least a part of an error correction code frame, the controller (7) of the first memory system is further configured to, in a case where the second memory system fails: generate first exclusive-logical-OR data by performing an exclusive-logical-OR operation on third data and the first data; and transmit the first exclusive-logical-OR data to the third memory system, and the controller (7) of the third memory system is further configured to, in the case where the second memory system fails: generate the second data by performing an exclusive-logical-OR operation on the first exclusive logical-OR data and the parity; and transmit the generated second data to a memory system that is replaced from the failed second memory system.