RAID Storage Controller Intermediate Parity Buffering
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Solution Overview
Problem
The performance of storage devices using RAID technology degrades due to increased load and latency as the amount of data increases, resulting from the complexity of dividing data into chunks and generating parity, which affects the reliability and efficiency of data storage operations.
Innovation Solution
A storage device configuration that includes multiple memories and a controller, which buffers data chunks and generates intermediate parities to optimize data storage operations, reducing the need for frequent loading and storing of data between cache and buffer memories, thereby decreasing latency and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RAID technology is used to store data with parity generation, then data reliability is improved, but processing load and latency increase as data amount increases
Solution Approach 1:
The patent divides parity generation into multiple stages: first generating intermediate parity for partial data chunks, then generating final parity for remaining chunks. This segmentation allows parallel processing of different data portions, reducing overall latency while maintaining RAID reliability through systematic parity distribution across storage devices.
Solution Approach 2:
The patent performs preliminary parity generation by creating intermediate parity for the first plurality of data chunks before processing the second plurality of chunks. This preliminary action enables overlapping operations where intermediate parity can be stored and utilized while subsequent data processing occurs, reducing total processing time without compromising data integrity.
2Productivity
If data is divided into chunks and distributed across multiple storage areas, then storage efficiency is improved, but the complexity of parity generation increases
Solution Approach 1:
The patent segments the data storage system into multiple independent chunks that can be processed separately. Each chunk undergoes independent parity generation using the same standardized process, which simplifies the overall complexity by breaking down a large complex operation into multiple smaller, manageable, and repeatable units.
Solution Approach 2:
The patent changes the processing parameters by introducing intermediate parity as a temporary state variable. This intermediate parity serves as a computational shortcut that reduces the complexity of final parity generation, allowing the system to handle distributed chunks more efficiently without increasing overall system complexity.
3Speed
If intermediate parity is buffered in cache memory, then access speed is improved, but cache memory capacity is consumed
Solution Approach 1:
The patent implements a strategy where intermediate parity is temporarily stored in cache memory during processing, then discarded from cache after being written to buffer memory. This allows the system to utilize fast cache memory for temporary intermediate results without permanently consuming cache capacity, as the same cache space can be reused for subsequent intermediate parity operations.
Solution Approach 2:
The patent introduces buffer memory as an intermediary storage layer between cache memory and final storage. This intermediary allows intermediate parity to be transferred from fast cache to slower buffer memory, freeing up cache capacity while maintaining processing speed through the use of cache for active computation.
Data Source
AI summary
A storage device includes a plurality of first memories, a controller, and a second memory. The controller controls the first memories such that first and second data chunks associated with target data are distributively stored in the plurality of first memories. The controller generates a first intermediate parity using the first data chunk, which is processed immediately before the second data chunk. When the second data chunk is not a data chunk which is processed last in connection with the target data and the first intermediate parity is buffered in the second memory, the controller generates a second intermediate parity using the first intermediate parity buffered in the second memory and the second data chunk, and outputs the second intermediate parity to the second memory to be buffered.