RAID Parity Computation via Firmware Hardware Scheduler

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Solution Overview

Problem

RAID storage systems face computational overload and inefficiency in computing redundancy information, particularly in RAID levels 5 and 6, due to the high load on general-purpose processors and limitations of special-purpose circuits.

Innovation Solution

A storage controller that combines a firmware parity engine (FPE) and a hardware parity engine (HPE), with a scheduler element to dynamically select the most suitable engine for redundancy computation based on operating conditions, optimizing the processing of redundancy information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a general purpose processor is used for redundancy computation, then device complexity is reduced, but computational load and processing time increase significantly

Engineering Contradiction:
Improvecontroller architecture complexityVSAvoidredundancy computation speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The redundancy computation function is segmented into two independent execution paths: a software-based firmware parity engine and a hardware-based parity engine. Each engine can operate independently, allowing the system to divide the computational workload between software and hardware domains, thereby reducing the burden on the general purpose processor while maintaining architectural flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A scheduler element is introduced as an intermediary component that manages the workload distribution between the firmware parity engine and the hardware parity engine. The scheduler receives redundancy computation requests and directs them to the appropriate engine based on system state, enabling coordinated operation of both execution paths without requiring direct integration between them.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If a special purpose circuit is used for redundancy computation, then redundancy computation speed improves, but device complexity and cost increase

Engineering Contradiction:
Improveredundancy computation speedVSAvoidcontroller architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system merges two different execution approaches (software and hardware parity engines) into a unified redundancy computation framework. Both engines process the same redundancy computation requests and can operate in parallel or sequentially, combining the advantages of software flexibility and hardware speed while sharing common control logic through the scheduler element.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The scheduler element serves multiple functions: it manages workload distribution, monitors system state, selects the appropriate engine for each computation request, and coordinates between the firmware and hardware parity engines. This multi-functional design reduces overall system complexity by consolidating control logic in a single component rather than requiring separate management mechanisms.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If the hardware parity engine is used for all redundancy computations, then computation speed is maximized, but adaptability to varying data patterns and operating conditions decreases

Engineering Contradiction:
Improveredundancy computation speedVSAvoidadaptability to data patterns
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The system dynamically selects which parity engine to use based on real-time operating conditions, data patterns, and system state. The scheduler element continuously monitors the workload characteristics and directs computation requests to the most suitable engine, enabling the system to adapt to varying conditions such as different data access patterns, RAID configurations, and hardware availability without requiring manual reconfiguration.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8756371B2Methods and apparatus for improved raid parity computation in a storage controller
Publication Date: 2014.06.17 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8756371B2 patent drawing
  • US8756371B2 patent drawing
  • US8756371B2 patent drawing

AI summary

Methods and apparatus for improved calculation of redundancy information in RAID storage controllers. Features and aspects hereof provide for a firmware/software element (FPE) for generating redundancy information in combination with a custom logic circuit (HPE) designed to generate redundancy information. A scheduler element operable on a processor of a storage controller along with the FPE determines which of the FPE and HPE is best suited to rapidly complete a new redundancy computation operation and activates or queues the new operation for performance by the selected component.