RAID Parity Calculation in Flash Memory SSDs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The performance penalty caused by the calculation of RAID 5 in SSD storage systems and the need to reduce the logical area of RAID 5 to meet the downsizing requirements of the control unit in flash memory-based storage systems.
Innovation Solution
A method and system that utilize a RAID processor to efficiently calculate and write parity check codes by submitting check code scheduling instructions, reading and writing data blocks in a manner that allows for time interleaving and asynchronous operations, with a data block pointer to record input positions and a parity check code buffer to store results, ensuring accurate and distributed calculation and writing of RAID 5 without deadlocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RAID 5 parity calculation is implemented in traditional SSD controllers, then data protection capability is improved, but controller logical area increases and performance penalty occurs
Solution Approach 1:
The patent segments the RAID 5 parity calculation function into independent processing units distributed across multiple cores. Each processing unit handles specific data blocks independently, allowing parallel computation without requiring a large centralized logical area in the controller. This segmentation enables the system to achieve data protection while maintaining a compact controller design.
Solution Approach 2:
The patent introduces an intermediary buffer memory structure that temporarily stores data blocks during parity calculation. This buffer acts as a mediator between the flash memory interface and the processing units, enabling asynchronous operations and reducing the logical area requirements of the controller by avoiding the need for large on-chip memory resources.
2Measurement precision
If traditional synchronous RAID parity calculation is used, then calculation accuracy is ensured, but writing speed decreases due to sequential processing
Solution Approach 1:
The patent implements preliminary action by pre-organizing data blocks into raid groups and pre-allocating processing tasks to different cores before actual parity calculation begins. This preparation enables subsequent parallel processing to proceed efficiently while maintaining accuracy through predetermined calculation sequences and verification mechanisms.
Solution Approach 2:
The patent introduces dynamic task scheduling that adapts the parity calculation process based on real-time system state. Multiple processing units dynamically allocate and execute parity calculation tasks in parallel, with the ability to adjust calculation depth and parallelism levels. This dynamic approach maintains calculation accuracy through coordinated verification while significantly improving writing speed through concurrent processing.
3Measurement precision
If data blocks are processed in strict sequence, then calculation correctness is maintained, but performance is reduced due to inability to exploit parallelism
Solution Approach 1:
The patent segments the RAID group data blocks into multiple independent processing units, each assigned to different processor cores. This segmentation allows parallel processing of different data blocks while maintaining calculation correctness through structured verification mechanisms that validate results after parallel computation.
Solution Approach 2:
The patent implements feedback mechanisms where processing units report their calculation results and status back to a coordination module. This feedback enables the system to verify calculation correctness in real-time while maintaining parallel execution, allowing the system to detect and correct any errors without requiring strict sequential processing.
4Stability of the object's composition
If flash memory units are accessed sequentially for parity writing, then data consistency is ensured, but writing throughput is limited
Solution Approach 1:
The patent implements dynamic writing strategies that adapt to the state of flash memory units. When multiple units are available, the system dynamically switches to parallel writing mode to maximize throughput. When units are occupied or in erasure state, the system dynamically adjusts to sequential access patterns, maintaining data consistency through coordinated write management and verification.
Solution Approach 2:
The patent performs preliminary actions by pre-checking the availability state of flash memory units before initiating parity writing. This allows the system to plan and execute parallel writes when conditions permit, while automatically falling back to sequential access when units are unavailable, thereby optimizing throughput without compromising data consistency.
Data Source
AI summary
A storage system for constructing RAID on the basis of flash memory comprises: one or more RAID processors and a plurality of flash memories. The RAID processor comprises a plurality of read-and-write processing units, a data block pointer unit, a data block counter and a parity check code buffer. One read and write processing unit can control one or more flash memory units. A method for constructing RAID in a storage system on the basis of flash memory can realize the function of RAID in a very small logic area and approximately negligible time and realize the unification of the function and performance of a storage system such as an enterprise-level SSD.