RAID Parity Computation Offload via Accelerator Memory
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Solution Overview
Problem
Existing RAID systems require significant computational overhead from the CPU to compute parity information, which can burden the central processing unit.
Innovation Solution
A system and method that offloads the parity computation from the CPU by using an accelerator processor and DMA circuits to perform parity calculations directly on data stored in an accelerator memory, reducing the need for CPU involvement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CPU performs parity calculation directly, then the parity computation is accurate and reliable, but the CPU processing overhead increases significantly
Solution Approach 1:
The patent extracts the parity computation function from the CPU and implements it in hardware logic within the storage controller. This separates the computationally intensive parity calculation task from the general-purpose CPU, allowing the CPU to focus on higher-level management tasks while the hardware logic handles the repetitive parity operations efficiently and reliably.
Solution Approach 2:
The patent introduces a dedicated parity computation module as an intermediary between the CPU and storage devices. This module receives data from the CPU, performs parity calculations using optimized hardware logic, and returns results to the CPU, thereby reducing the CPU's direct involvement in computationally intensive operations.
2Device complexity
If parity calculation is performed using software-based CPU processing, then the system is simpler to implement, but the processing speed and computational efficiency decrease
Solution Approach 1:
The patent replaces the software-based CPU processing mechanism with a hardware-based computation logic in the storage controller. This substitution leverages the inherent speed advantage of hardware logic over software execution, achieving faster parity computation while maintaining acceptable system complexity through integrated hardware design.
3Ease of operation
If the CPU is heavily involved in parity computation, then all processing steps can be coordinated centrally, but the CPU becomes a bottleneck for other tasks
Solution Approach 1:
The patent segments the storage control functions by separating parity computation from general CPU tasks. The storage controller handles parity operations independently through dedicated hardware logic, while the CPU focuses on data management and coordination. This segmentation eliminates the CPU bottleneck while maintaining centralized coordination through the storage controller's own control logic.
Data Source
AI summary
A redundant disk array may include redundant information to facilitate rebuilding the array in the event of a disk failure. A host processor may allocate buffers in an accelerator memory. Data may be moved from one or more storage devices to the buffers. An accelerator engine may perform parity calculations required to rebuild the array based on data in the buffers without requiring a host CPU to perform the parity calculation.