Degraded RAID Data Reconstruction Using PCIe Peer-to-Peer DMA
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Solution Overview
Problem
Conventional RAID systems rely heavily on host CPU and memory for parity generation and data reconstruction, leading to bandwidth consumption and performance bottlenecks, especially with high-performance NVMe drives, and existing hardware RAID architectures are inefficient for large data strips.
Innovation Solution
Utilize an accelerator engine with PCIe peer-to-peer direct memory access (DMA) capabilities to reconstruct data from a degraded RAID volume, offloading computations from the host CPU and using the accelerator engine's memory as a buffer, reducing the need for host memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional RAID systems use host CPU and memory for parity generation and data reconstruction, then data reconstruction can be performed, but host memory bandwidth is consumed and performance bottlenecks occur
Solution Approach 1:
The patent extracts the data reconstruction function from the host system and places it in a dedicated RAID controller. The controller includes local memory and processing units that independently perform parity calculations and data reconstruction without consuming host memory bandwidth or CPU resources, thereby resolving the contradiction between reconstruction capability and host resource consumption
Solution Approach 2:
The RAID controller acts as an intermediary between the host and storage devices. It handles all computationally intensive operations including parity generation and data reconstruction using its own embedded resources, serving as a mediator that protects the host from bandwidth consumption while maintaining full RAID functionality
2Ease of manufacture
If software stacks use CPU instructions or AVX instructions for XOR operations, then parity generation can be performed, but significant host and memory controller bandwidth is consumed
Solution Approach 1:
The patent replaces software-based CPU instructions (including AVX) with hardware-based XOR operation units in the RAID controller. This hardware implementation performs parity generation operations directly in the controller without requiring host CPU intervention or memory controller bandwidth, eliminating the contradiction between operational capability and bandwidth consumption
3Adaptability or versatility
If traditional hardware RAID architecture is used, then data storage and retrieval can be performed, but performance bottlenecks occur when scaling with high-performance NVMe drives
Solution Approach 1:
The patent implements a dynamic architecture in the RAID controller that can adapt to different storage device types including NVMe drives. The controller uses PCIe interfaces and programmable processing units that can dynamically adjust to the performance characteristics of connected devices, enabling full utilization of NVMe speeds while maintaining RAID functionality
4Ease of operation
If host memory is used for transfer buffers during data reconstruction, then data can be reconstructed, but the host's ability to execute other applications is impaired
Solution Approach 1:
The patent segments the memory resources by providing the RAID controller with dedicated local memory for all reconstruction operations. This segmentation isolates reconstruction buffer requirements from host memory, allowing the host to execute applications without interference while the controller independently manages its own memory resources for data reconstruction
Data Source
AI summary
A system and method for reconstructing data from a degraded RAID storage device using an accelerator engine is disclosed. An article of manufacture may include a non-transitory memory having machine-readable instructions that, when executed by a processor, cause the processor to send a first command to a first storage device and a second storage device to trigger the first and second storage devices to write strip data to a memory in an accelerator engine. The instructions may also cause the processor to send a second command to the accelerator engine to perform an operation on the written strip data, the operation to reconstruct data stored on a third failed storage device. The first, second, and third storage devices may be part of a RAID volume. Further, the instructions may cause the processor to receive an output of the operation from the accelerator engine.