RAID Write Path Using Device-Side Parity Buffering
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Solution Overview
Problem
The existing storage system's process of storing intermediate parity in both cache memory and nonvolatile memory increases the load on the storage controller, leading to performance bottlenecks and potential data loss in case of system faults.
Innovation Solution
A storage system with a processor, buffer memory, and cache memory, where the processor manages data writes across multiple storage devices, transferring data through a communication network, and uses a RAID group configuration to distribute data and parity across multiple storage media, reducing the load on the cache memory and enhancing fault tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If intermediate parity is stored in both cache memory and nonvolatile memory, then data reliability is improved, but the load on storage controller increases and performance deteriorates
Solution Approach 1:
The patent extracts the intermediate parity storage function from the storage controller to the storage devices themselves. Storage devices autonomously generate and store intermediate parity in their own memory, removing this burden from the storage controller and reducing its load while maintaining data reliability through distributed parity storage.
Solution Approach 2:
Storage devices perform self-service by autonomously generating intermediate parity and managing their own parity storage without requiring the storage controller to intervene in every parity operation. This self-service capability reduces controller workload while ensuring parity data is properly maintained for fault tolerance.
2Speed
If intermediate parity is stored in cache memory only, then access speed is improved, but data loss occurs in case of system fault
Solution Approach 1:
The patent segments the parity storage function across multiple storage devices rather than centralizing it in the storage controller's cache memory. Each storage device maintains its own intermediate parity locally, providing both fast access (since parity is locally available) and fault tolerance (since parity is distributed across multiple devices).
Solution Approach 2:
Each storage device maintains intermediate parity locally in its own memory, ensuring that parity data is readily accessible when needed while also being preserved locally even if the system controller fails. This local quality approach ensures both speed and reliability simultaneously.
3Ease of operation
If storage controller manages all parity operations centrally, then coordination is simplified, but the storage controller becomes a performance bottleneck
Solution Approach 1:
The patent segments the centralized parity management function into distributed operations at each storage device. Each device independently handles its own intermediate parity generation and storage, eliminating the coordination bottleneck at the storage controller while standard protocols maintain overall system coordination.
Solution Approach 2:
Standard communication protocols act as intermediaries between storage devices, enabling coordinated parity operations without requiring the storage controller to directly manage every parity operation. This intermediary layer maintains system-wide coordination while allowing local autonomy at each storage device.
Data Source
AI summary
A storage system has a RAID group configured by storage media, a system controller with a processor, a buffer memory coupled to storage devices and the processor by a communication network, and a cache memory coupled to the processor and the buffer memory by the network. A processor that stores first data, which is related to a write request from a host computer, in a cache memory, specifies a first storage device for storing data before update, which is data obtained before updating the first data, and transfers the first data to the specified first storage device. A first device controller transmits the first data and second data based on the data before update, from the first storage device to the system controller. The processor stores the second data in the buffer memory, specifies a second storage device, and transfers the stored second data to the specified second storage device.