RAID 4 Memory System with Tree-Like Interconnection for Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current computer memory systems face bottlenecks in data access time due to high latency in persistent storage media, particularly in large data sets, and the limitations of FLASH memory technologies, which are constrained by design and wear-out mechanisms, leading to performance issues and increased complexity in managing memory.
Innovation Solution
A memory system utilizing a RAID 4 architecture with a tree-like interconnection of memory modules, where data is striped across multiple modules, and a parity module is used for error correction and redundancy, allowing sequential writing and reading operations to minimize conflicts between read and write operations, and enabling efficient data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in persistent storage media (FLASH memory, disk), then data retention capability is improved, but data access time latency increases
Solution Approach 1:
The patent segments data into multiple stripes distributed across different FLASH memory modules. This allows the system to access different portions of data in parallel, reducing overall access latency while maintaining data retention through persistent storage. The segmentation enables concurrent read operations across multiple modules without requiring sequential access.
Solution Approach 2:
The patent introduces a new dimension of organization by arranging FLASH memory modules in a tree-like interconnection structure with multiple levels. This hierarchical arrangement allows data to be accessed through multiple paths and enables parallel operations at different levels of the tree, effectively reducing access latency while preserving data retention capabilities.
2Reliability
If sequential writing operations are performed on FLASH memory modules, then write operation completion is ensured, but read operations during writing are blocked
Solution Approach 1:
The patent divides the FLASH memory system into multiple independent modules organized in stripes. When one module is performing a sequential write operation, other modules remain available for read operations. This segmentation allows the system to maintain write reliability in the active module while preserving read productivity in other modules simultaneously.
Solution Approach 2:
The patent enables continuous useful action by allowing read operations to proceed concurrently with write operations in different modules. The tree-like interconnection structure ensures that while one module is completing its write sequence, other modules can service read requests, maintaining overall system productivity without compromising write completion reliability.
3Quantity of substance
If multiple memory modules are used for data storage, then storage capacity is improved, but system complexity increases
Solution Approach 1:
The patent segments the large storage system into multiple smaller, identical FLASH memory modules. Each module has the same structure and can be independently managed, which simplifies the overall system architecture despite the increased total capacity. The modular segmentation makes it easier to expand storage capacity by simply adding more identical modules rather than designing increasingly complex monolithic systems.
Solution Approach 2:
The patent creates universal, multi-functional memory modules that can serve multiple purposes: data storage, error correction through parity modules, and wear leveling. Each module is designed with the same capabilities, allowing them to be interchanged and managed uniformly. This universality reduces system complexity by eliminating the need for different specialized components while still achieving high storage capacity.
4Speed
If FLASH memory modules are used for persistent storage, then access speed is improved compared to mechanical devices, but wear-out mechanism reduces lifespan
Solution Approach 1:
The patent merges multiple FLASH memory modules into a unified RAID-like system where data is distributed across modules in stripes. This combination allows the system to maintain the high access speed of individual FLASH modules while distributing wear across all modules. The parity module provides additional redundancy that protects against wear-out failures, effectively extending the operational lifespan of the storage system.
Solution Approach 2:
The patent changes the operational parameters of the FLASH memory system by implementing sequential write operations that complete before subsequent writes to the same module begin. This parameter change allows read operations to occur during write completion periods, maximizing utilization of the high-speed FLASH memory while managing wear through controlled access patterns that extend module lifespan.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.