Rail-to-Rail Differential Buffer Input Stage With Constant Transconductance
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Solution Overview
Problem
Rail to rail differential buffer input stages face challenges in maintaining operational characteristics for varying common mode input voltages, especially under reduced power supply voltages and manufacturing process variations, leading to inefficiencies in transconductance and increased static current consumption.
Innovation Solution
The implementation of a rail to rail differential buffer input stage with n-type and p-type input differential pairs and dummy pairs of transistors, along with a dynamic reference voltage generator, which adjusts the transconductance by diverting tail current based on common mode input voltage, maintaining constant transconductance across varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed voltage divider is used to generate the intermediate voltage for switching dummy pairs, then the switching point is stable, but the resistance must be high which causes high static current consumption and large chip area
Solution Approach 1:
The patent replaces the fixed voltage divider with a dynamic voltage generation circuit that actively adjusts the intermediate voltage based on common mode input voltage levels. This dynamic approach allows the circuit to maintain proper switching points without requiring high resistance values, thereby reducing static current consumption while preserving stability through active control rather than passive resistance.
2Device complexity
If a fixed voltage divider is used to generate the intermediate voltage, then the circuit is simple, but it cannot adapt to manufacturing process variations on MOSFET characteristics
Solution Approach 1:
The patent implements feedback mechanisms where the dynamic voltage generation circuit continuously monitors the common mode input voltage and adjusts the intermediate voltage accordingly. This feedback loop enables the circuit to automatically compensate for manufacturing process variations in MOSFET characteristics, ensuring consistent switching points across different process corners without requiring complex calibration circuits.
Solution Approach 2:
The dynamic voltage generation circuit uses the common mode input voltage itself as a reference to generate the appropriate intermediate switching voltage. This self-service approach eliminates the need for external precise voltage references and allows the circuit to automatically adapt to process variations, maintaining proper operation across different manufacturing conditions.
3Adaptability or versatility
If the common mode input voltage varies over the whole voltage difference between power supply rails, then the input range is maximized, but maintaining constant transconductance becomes difficult without dummy pairs
Solution Approach 1:
The patent divides the input differential pair into multiple segments (n-type and p-type differential pairs) that are activated at different common mode voltage levels. By segmenting the input stage and using dummy pairs to control which segment is active, the circuit maintains constant transconductance across the full common mode voltage range, with each segment optimized for its specific operating region.
Solution Approach 2:
The dummy differential pairs act as intermediary elements that control the switching between n-type and p-type input differential pairs. These intermediary dummy pairs respond to common mode voltage changes and selectively activate or deactivate the main input pairs, ensuring smooth transitions and maintaining constant transconductance throughout the full input voltage range.
Data Source
AI summary
A rail to rail differential buffer input stage includes n-type and p-type input differential transistor pairs connected in voltage follower configuration to the power supply rails. A reference voltage generator includes a reference differential transistor pair generating a dynamic reference voltage relative to the common mode input voltage. Dummy n-type and p-type transistor pairs have current conducting paths connected in parallel with the input differential pairs and are controlled by the dynamic reference voltage to divert supply rail current away from and deactivate one of the associated input differential pairs when the common mode input voltage is further from the dynamic reference voltage than a threshold value. Both the dummy pairs conduct and both the input differential pairs are activated when the common mode input voltage is closer to the dynamic reference voltage VB than the threshold value so that the overall transconductance of the buffer input stage remains constant.