Rail Decoupling Circuits for Independent Power Sequencing
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Solution Overview
Problem
Integrated circuits with multiple power domains face reliability and functionality issues due to I/O pad circuits being controlled by unpowered core circuits, leading to increased design complexity and susceptibility to human error in power sequencing.
Innovation Solution
The method involves using an always on power domain to drive control inputs of I/O pad circuits with default values during power sequencing, decoupling them from core voltage rail behavior, allowing independent powering of core and I/O voltage rails without compromising I/O pad circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power sequencing requirements are established to ensure I/O pad circuits are controlled by powered core circuits, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the power domains by introducing an intermediate power domain that is distinct from both the core power domain and the I/O power domain. This intermediate domain contains control circuits that manage the power sequencing between core and I/O domains, thereby isolating the complexity of power management from the main functional blocks and reducing overall design complexity while maintaining reliability.
Solution Approach 2:
The patent introduces an intermediate power domain as a mediator between the core power domain and the I/O power domain. This intermediate domain contains control circuits that generate control signals to manage the power-up and power-down sequences, ensuring that I/O pad circuits are only controlled when core circuits are properly powered, thus improving reliability without requiring complex external sequencing circuits.
2Reliability
If sequencing circuits are added to automatically ensure power sequencing requirements are met, then reliability is improved, but device complexity and manufacturing time increase
Solution Approach 1:
The patent merges the power sequencing control functionality directly into the I/O pad circuit block by introducing an intermediate power domain that is integrated with the I/O domain. This integration eliminates the need for separate external sequencing circuits, thereby reducing manufacturing complexity and time while maintaining automatic power sequencing control for reliability.
Solution Approach 2:
The intermediate power domain contains control circuits that automatically monitor and manage the power states of both core and I/O domains, enabling the system to self-regulate power sequencing without external intervention. This self-service mechanism ensures reliability while simplifying the manufacturing process by eliminating manual configuration and external sequencing components.
3Adaptability or versatility
If manual selection and configuration of sequencing circuits is performed, then adaptability is improved, but human error increases and productivity decreases
Solution Approach 1:
The control circuits in the intermediate power domain automatically detect the power states of core and I/O domains and dynamically adjust control signals accordingly, eliminating manual configuration requirements. This self-service approach maintains adaptability to different power scenarios while significantly reducing design time and eliminating human error associated with manual sequencing circuit configuration.
Solution Approach 2:
The patent implements feedback mechanisms where control circuits continuously monitor the power states of core and I/O domains and automatically adjust control signals based on detected conditions. This feedback-driven automation provides adaptability to various power scenarios while eliminating manual configuration steps, thereby increasing productivity and reducing design time.
Data Source
AI summary
In various embodiments, rail decoupling circuits that are powered by an always on voltage rail allow a core voltage rail to power up independently of an I/O voltage rail without jeopardizing I/O pad circuits that are powered by the I/O voltage rail. In an embodiment, when the always on voltage rail is powered-up and a chip reset signal is asserted, the rail decoupling circuits drive control inputs of the I/O pad circuits based on default values. When the chip reset signal is de-asserted, the rail decoupling circuits drive the control inputs of the I/O pad circuits based on signals received from circuits powered by the core voltage rail. Because the rail decoupling circuits maintain control of the I/O pad circuits until the chip-reset is de-asserted, the core voltage rail can power up at any time before the chip-reset signal is de-asserted irrespective of when the I/O voltage rail powers up.