Rail-to-rail buffer for LDO gate drive stability
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Solution Overview
Problem
Conventional low-dropout (LDO) voltage regulators face stability issues due to conflicting requirements for the gate terminal of the pass-FET, where n-channel source followers cannot pull up the gate to the supply voltage and p-channel source followers cannot pull down to ground, affecting the regulator's ability to maintain output voltage stability across varying load currents.
Innovation Solution
A low-dropout voltage regulator design incorporating a rail-to-rail buffer circuit with a resistive bypass arrangement allows the pass-FET to be fully pulled up or down, using a buffer signal to adjust the gate terminal of the pass-FET, enabling stable operation across different load currents by detecting sense voltage drops and adjusting the output voltage accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an n-channel source follower buffer is used to drive the gate of the PMOS pass-FET, then the buffer can pull down the gate to ground at high load currents, but it cannot pull up the gate to the supply voltage at zero load currents
Solution Approach 1:
The patent introduces a dual-buffer system where an n-channel source follower buffer and a p-channel source follower buffer work together as intermediaries. The n-channel buffer handles the pull-down function while the p-channel buffer handles the pull-up function, allowing the gate terminal to achieve full rail-to-rail voltage range adaptation across all load conditions.
Solution Approach 2:
The buffering function is segmented into two specialized buffers: an n-channel source follower buffer for pull-down operations and a p-channel source follower buffer for pull-up operations. This segmentation allows each buffer to be optimized for its specific function, resolving the limitation of using a single buffer type for both high and low load current conditions.
2Ease of operation
If a PMOS source follower buffer is used to drive the gate of the PMOS pass-FET, then the buffer can pull up the gate to the supply voltage at zero load currents, but it cannot pull down the gate to ground at high load currents
Solution Approach 1:
The patent introduces a dual-buffer system where an n-channel source follower buffer and a p-channel source follower buffer work together as intermediaries. The n-channel buffer handles the pull-down function while the p-channel buffer handles the pull-up function, allowing the gate terminal to achieve full rail-to-rail voltage range adaptation across all load conditions.
Solution Approach 2:
The buffering function is segmented into two specialized buffers: an n-channel source follower buffer for pull-down operations and a p-channel source follower buffer for pull-up operations. This segmentation allows each buffer to be optimized for its specific function, resolving the limitation of using a single buffer type for both high and low load current conditions.
3Reliability
If the rail-to-rail buffer circuit is always active, then the gate terminal can be fully pulled up or down across all load conditions, but current consumption increases unnecessarily at low load currents
Solution Approach 1:
The patent implements dynamic control of the rail-to-rail buffer circuit by enabling it only when load current exceeds a threshold level. This dynamic activation ensures the buffer circuit is active only when needed for maintaining output voltage stability under high load conditions, while remaining inactive during low load conditions to minimize current consumption.
Solution Approach 2:
The patent changes the operational state parameter of the buffer circuit based on load current conditions. A threshold detection mechanism monitors the load current and switches the buffer circuit between active and inactive states, optimizing the balance between output voltage stability and current consumption across different operating conditions.
Data Source
AI summary
A low-dropout voltage regulator is arranged to convert an input voltage to an output voltage. The low-dropout voltage regulator comprises: an error amplifier circuit portion arranged to produce an error signal proportional to a difference between a sense voltage (Vsense) and a reference voltage (Vref), wherein the sense voltage is derived from the output voltage; a pass field-effect-transistor (MP) connected to the input voltage; and a rail-to-rail buffer circuit portion connected between the input voltage (VDD) and ground. The rail-to-rail buffer circuit portion comprises: a buffer input arranged to receive the error signal; a buffer output arranged to apply a buffer signal to the gate terminal of the pass field-effect-transistor, wherein the buffer signal is a buffered version of the error signal; and a resistive bypass arrangement (Rbypass) connected between the buffer input and the buffer output.