Rail-to-rail comparator input offset control circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In peak current mode control (PCMC) applications, rail-to-rail comparators with n-type and p-type metal oxide semiconductor input transistor pairs experience varying offsets, leading to abrupt slope errors and instability in the control loop due to different offsets, affecting the stability and accuracy of the comparator.
Innovation Solution
An input offset control circuit with a first and second input circuit, configured to operate within specific common mode voltage ranges, adjusts input currents based on voltage variations, ensuring smooth transitions and maintaining the slope of the ramp signal by reducing and increasing currents accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a rail-to-rail comparator with n-type and p-type metal oxide semiconductor input transistor pairs is used, then the common mode voltage range is extended, but the input offset varies abruptly at the switch-over point causing slope errors and control loop instability
Solution Approach 1:
The input stage is segmented into a first input circuit with p-type metal oxide semiconductor transistors for a first common mode voltage range and a second input circuit with n-type metal oxide semiconductor transistors for a second common mode voltage range. This segmentation allows each circuit to operate optimally within its designated voltage range, preventing the abrupt offset variations that occur when switching between transistor types in a traditional rail-to-rail comparator.
Solution Approach 2:
Each input circuit is designed with specific transistor types optimized for its designated common mode voltage range. The first input circuit uses p-type transistors optimized for lower voltage ranges, while the second input circuit uses n-type transistors optimized for higher voltage ranges. This local optimization ensures consistent offset characteristics within each range while maintaining extended overall voltage coverage.
2Adaptability or versatility
If the common mode voltage range is extended using traditional rail-to-rail comparator design, then voltage adaptability is improved, but slope errors occur due to varying input offset
Solution Approach 1:
The comparator input stage is divided into separate first and second input circuits, each handling a specific common mode voltage range with dedicated transistor types. This segmentation prevents the mixing of n-type and p-type transistor operations that causes offset variations and slope errors in traditional designs.
Solution Approach 2:
The patent changes the operating parameters by maintaining consistent transistor type within each segmented circuit rather than switching types across the voltage range. This parameter consistency ensures that the input offset remains stable and the ramp signal slope remains accurate throughout the extended common mode voltage range.
3Device complexity
If a single input circuit with switching transistor pairs is used for rail-to-rail operation, then device complexity is reduced, but input offset stability deteriorates due to switch-over point variations
Solution Approach 1:
Instead of using a single input circuit with switching transistor pairs, the patent segments the input stage into two separate input circuits, each dedicated to a specific common mode voltage range. This segmentation eliminates the need for dynamic switching between transistor types, thereby maintaining input offset stability while achieving rail-to-rail operation.
Solution Approach 2:
The patent introduces an intermediate architecture where two parallel input circuits operate simultaneously, each optimized for its voltage range. This intermediary structure avoids the direct switching between n-type and p-type transistors that causes offset instability, providing a smooth transition across the common mode voltage range.
Data Source
AI summary
Several circuits and methods for input offset control are disclosed. In an embodiment, a input offset control circuit includes a first input circuit and a second input circuit. The first input circuit is configured to operate within first common mode voltage range, configured to provide first input current, and configured to vary the first input current upon or subsequent to a variation of a voltage level in the first common mode voltage range. The second input circuit is coupled to the first input circuit and is configured to operate within second common mode voltage range, configured to provide a second input current, and configured to vary the second input current based on variation of the voltage level in the second common mode voltage range. Upon or subsequent to increasing the common mode voltage, the first input current is reduced and the second input current is increased.