RAIM Memory Channel Refresh Staggering for Low-Latency Fetch

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Solution Overview

Problem

In multi-channel memory systems, the alignment of refresh operations across multiple channels leads to significant delays due to large refresh times, particularly as DRAM capacity and performance increase, causing penalties for fetch operations when a rank is being refreshed.

Innovation Solution

Implementing a staggered refresh method where the same rank is not refreshed simultaneously across channels, using a rank refresh channel mark to ignore the contents of a channel during refresh and releasing data to the memory controller to save latency associated with refresh penalties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If refresh operations are aligned across multiple channels, then memory management is simplified, but fetch operations experience significant delays due to large refresh times

Engineering Contradiction:
Improvememory managementVSAvoidfetch operation delay
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent segments the refresh operations across different channels by introducing channel-specific refresh indicators. Each channel can be independently marked as refreshing or non-refreshing, allowing the system to divide the monolithic refresh operation into channel-specific segments. This enables fetch operations to proceed on non-refreshing channels while refresh operations occur on other channels, resolving the contradiction between simplified management and reduced delay.

Inventive Principle:
Principle #1Segmentation

2Productivity

If all channels are used for data fetching, then system throughput is maximized, but latency increases when a rank is being refreshed

Engineering Contradiction:
Improvesystem throughputVSAvoidfetch latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements periodic refresh actions on different channels in a staggered manner. By periodically switching which channel undergoes refresh operations and which channels perform fetch operations, the system maintains continuous throughput while managing refresh latency. The refresh indicator is updated periodically to reflect the current channel's refresh status, allowing other channels to service fetch requests during their non-refresh periods.

Inventive Principle:
Principle #19Periodic action

3Reliability

If a channel is marked as unavailable due to degradation, then data integrity is maintained, but system capacity is reduced

Engineering Contradiction:
Improvedata integrityVSAvoidsystem capacity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the status parameter of degraded channels from completely unavailable to conditionally usable. By introducing a degradation indicator and implementing error correction mechanisms, the system can dynamically adjust the operational parameters of degraded channels. This allows the channel to remain in service with modified access patterns or error tolerance levels, maintaining data integrity through correction while preserving system capacity that would otherwise be lost.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11609817B2Low latency availability in degraded redundant array of independent memory
Publication Date: 2023.03.21 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11609817B2 patent drawing
  • US11609817B2 patent drawing
  • US11609817B2 patent drawing

AI summary

A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.