Raised Bitline Memory Cell Channel Length Scaling
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Solution Overview
Problem
Conventional charge trapping dielectric flash memory devices face performance degradation due to short channel effects when downscaling, leading to inadequate data retention and electrical characteristics, particularly when the gate electrode width is comparable to the buried bitlines, resulting in inefficient channel length scaling.
Innovation Solution
The method involves forming raised bitlines with distinct lower and upper portions using different processes, where the lower portion is formed to minimize dopant diffusion and the upper portion is highly conductive, optimizing bitline functionality and channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are downscaled to increase data storage density, then storage capacity per unit area is improved, but short channel effects worsen due to inadequate gate control over the active channel region
Solution Approach 1:
The patent transitions from planar buried bitlines to vertically raised bitlines, adding a vertical dimension to the bitline structure. This dimensional change allows the bitlines to extend above the substrate surface and gate electrode top surface, effectively increasing the channel length without increasing the lateral footprint, thus maintaining high storage density while improving gate control
Solution Approach 2:
The raised bitline structure is segmented into multiple portions: a lower portion formed by selective epitaxial growth and an upper portion formed by polysilicon deposition. This segmentation allows different formation processes to be applied to different portions, optimizing each segment's properties for its specific function while collectively solving the short channel effect problem
2Area of stationary object
If the gate electrode width is made comparable to the buried bitlines width, then device area is reduced, but channel length scaling efficiency deteriorates
Solution Approach 1:
By raising the bitlines vertically above the substrate and gate electrode surfaces, the patent extends the channel length in the vertical dimension rather than requiring proportional reduction in lateral dimensions. This allows the gate electrode width to remain comparable to the buried bitline width while still achieving effective channel length scaling through the vertical extension of the raised bitline portions
3Ease of manufacture
If raised bitlines are formed using a single process, then manufacturing complexity is reduced, but bitline functionality is insufficient due to inability to optimize both dopant diffusion control and conductivity
Solution Approach 1:
The raised bitline is segmented into a lower portion and an upper portion, each formed by a different process. The lower portion uses selective epitaxial growth to minimize dopant diffusion into the channel region, while the upper portion uses polysilicon deposition to provide high conductivity. This segmentation resolves the contradiction by allowing each segment to be optimized for its specific functional requirement
Solution Approach 2:
Different portions of the bitline are given different local qualities through different formation processes. The lower portion near the channel region is optimized for dopant diffusion control, while the upper portion is optimized for electrical conductivity. This local differentiation allows the bitline to simultaneously achieve both objectives that cannot be met by a single uniform structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the scalability of memory devices by increasing the effective channel length, improving charge separation and reducing short channel effects, while maintaining data retention and performance.
Implementation Method 1
forming a lower portion of each bitline using a first forming process
Implementation Method 2
forming an upper portion of each bitline using a second forming process
Data Source
AI summary
A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of raised bitlines, where the bitlines have a lower portion formed by a first process and an upper portion formed by a second process.