Raised E-Fuse Structure for Thermal Isolation in SOI CMOS
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional electrically programmable fuses in semiconductor devices face challenges with complex manufacturing, especially in aggressive downscaling to sub 28 nm or sub 22 nm VLSI Circuits CMOS technologies, due to issues like insufficient electrical isolation, high current demands, and poor thermal isolation, leading to reliability concerns.
Innovation Solution
The development of a semiconductor device with a raised e-fuse structure integrated in a SOI configuration, where silicided semiconductor regions are formed on an insulating layer, allowing for reduced programming currents and improved thermal isolation through a 'bottleneck' configuration that concentrates current density, facilitating reliable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional e-fuse structures are used in aggressive downscaling to sub 28 nm or sub 22 nm CMOS technologies, then device miniaturization is achieved, but electrical isolation becomes insufficient and reliability deteriorates
Solution Approach 1:
The patent transitions from a planar e-fuse structure to a raised three-dimensional structure. The fuse body is formed as a raised region extending from the substrate surface, creating vertical dimensionality that improves electrical isolation between adjacent fuses and between the fuse and surrounding circuitry, while maintaining small footprint area for continued miniaturization.
Solution Approach 2:
The e-fuse structure is segmented into distinct functional regions: a raised fuse body region, a silicided region, and an isolation region. This segmentation allows each region to be optimized independently - the raised body provides isolation, the silicided region provides the fuse function, and the isolation region enhances electrical separation, collectively resolving the contradiction between miniaturization and isolation.
2Volume of moving object
If conventional e-fuse structures are used in aggressive downscaling, then device miniaturization is achieved, but thermal isolation becomes poor and reliability deteriorates
Solution Approach 1:
The raised three-dimensional structure of the fuse body creates vertical separation from the substrate and surrounding circuitry. This vertical dimensionality provides thermal isolation by increasing the thermal path length and reducing heat transfer to the substrate, preventing thermal interference while maintaining compact planar footprint for continued miniaturization.
3Ease of manufacture
If conventional e-fuse structures are used, then manufacturing process is simple, but programming current demand is high and reliability deteriorates
Solution Approach 1:
The silicided region is formed locally at specific portions of the raised fuse body where current concentration is desired. This localized silicidation creates a low-resistance path that concentrates the programming current precisely where needed, reducing the overall programming current demand while maintaining manufacturing simplicity through integration with existing silicidation processes.
4Reliability
If raised semiconductor regions are formed and silicidation is performed, then programming current is reduced and reliability improves, but device complexity increases
Solution Approach 1:
The e-fuse formation process is merged with the existing FET manufacturing process flow. The raised semiconductor regions are formed using the same epitaxial growth and silicidation steps that are already employed for FET source and drain regions. This integration reduces device complexity by consolidating process steps and utilizing existing manufacturing capabilities rather than adding separate dedicated processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable operation with low programming currents and efficient thermal management, addressing the limitations of conventional e-fuses by integrating the e-fuse formation within the FET manufacturing process, resulting in improved performance and reliability in advanced integrated circuits.
Implementation Method 1
improved thermal isolation through a 'bottleneck' configuration that concentrates current density
Implementation Method 2
improved thermal isolation through a 'bottleneck' configuration
Data Source
AI summary
A method of manufacturing a semiconductor device with a fuse is provided including the steps of providing a semiconductor-on-insulator (SOI) structure including an insulating layer and a semiconductor layer formed on the insulating layer, forming a first raised semiconductor region on the semiconductor layer and a second raised semiconductor region on the semiconductor layer adjacent to the first semiconductor region, and performing a silicidation process of the first and second raised semiconductor regions to form a first at least partially silicided raised semiconductor region with a first silicided portion and a second at least partially silicided raised semiconductor region with a second silicided portion.