Raised Epitaxial Layer for Flash Memory Write Disturb
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Solution Overview
Problem
In semiconductor devices with flash memory, accidental erasure of information can occur during the write operation due to hot hole injection or floating electric potential in the channel region, caused by steep or gentle variations in impurity concentration profiles between diffusion layers and LDD regions, leading to write disturb in unselected bits.
Innovation Solution
The semiconductor device incorporates a memory transistor with a raised epitaxial layer and a diffusion layer having a higher impurity concentration, where the diffusion layer is primarily located in the raised epitaxial layer, and a method of manufacturing that includes forming a memory transistor with a gate insulating film and a charge storage layer, and implanting impurities to create regions with specific impurity concentrations to suppress write disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the impurity concentration profile steeply varies between the diffusion layer and the LDD region, then the hot hole is generated due to potential difference, but the information may be accidentally erased due to hot-hole injection into the charge storage layer
Solution Approach 1:
The patent applies local quality by creating a raised epitaxial layer structure that locally modifies the impurity concentration distribution. The diffusion layer is positioned within the raised epitaxial layer with a higher impurity concentration, while the LDD region maintains a lower impurity concentration. This localized structural modification creates a gentle impurity concentration gradient that reduces hot hole generation while maintaining effective charge storage functionality.
Solution Approach 2:
The patent changes the impurity concentration parameter by positioning the diffusion layer with higher impurity concentration within the raised epitaxial layer, while maintaining a lower impurity concentration in the LDD region. This parameter modification creates a controlled impurity concentration profile that mitigates hot hole generation and prevents accidental information erasure during write operations.
2Object-affected harmful factors
If the impurity concentration profile gently varies between the diffusion layer and the LDD region, then the electric potential of the channel region may float due to depleted layer extending from the diffusion layer
Solution Approach 1:
The patent introduces a vertical dimension by forming a raised epitaxial layer structure. The diffusion layer is positioned within this raised structure, creating a three-dimensional impurity concentration distribution. This dimensional approach allows the depleted layer to extend vertically rather than horizontally into the channel region, preventing electric potential floating while maintaining gentle impurity concentration variation.
Solution Approach 2:
The raised epitaxial layer structure creates local quality differences in the semiconductor device. The diffusion layer within the raised structure has higher impurity concentration, while the LDD region maintains lower concentration. This localized modification prevents depleted layer extension into the channel region, stabilizing electric potential while reducing hot hole generation.
3Manufacturing precision
If the gate length of the gate electrode is reduced, then the manufacturing precision is improved, but the electric potential of the channel region may easily float leading to accidental erasure
Solution Approach 1:
The raised epitaxial layer structure with the diffusion layer positioned within it creates local quality modifications that prevent electric potential floating in the channel region. This structural approach allows for reduced gate length and improved manufacturing precision while maintaining channel region electric potential stability through the controlled impurity concentration profile.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces accidental erasure of information in unselected bits by controlling the impurity concentration profiles, thereby minimizing write disturb and improving retention characteristics through high-temperature hydrogen anneal processing.
Implementation Method 1
electron is injected from the well region into the charge storage layer to write the information
Implementation Method 2
hole is injected from a gate electrode into the charge storage layer to erase the information
Implementation Method 3
hot hole may be generated due to such a potential difference. The hot hole is injected into the charge storage layer
Implementation Method 4
improving retention characteristics through high-temperature hydrogen anneal processing
Data Source
AI summary
In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.