Raised-Extension Transistors for High-Breakdown-Voltage NAND Flash
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Solution Overview
Problem
Existing transistors in NAND flash memory devices require high surface area due to the need for lightly-doped extension regions, which increases the footprint and may not efficiently handle high breakdown voltages required for programming memory cells.
Innovation Solution
The use of raised extension regions in field-effect transistors (FETs) to facilitate high breakdown voltages while reducing the transistor footprint, utilizing smaller semiconductor areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lightly-doped extension regions are used to achieve high breakdown voltages, then transistor reliability is improved, but transistor footprint increases
Solution Approach 1:
The patent transitions from planar extension regions to vertically-raised extension regions, utilizing the third dimension (height) to provide the necessary breakdown voltage handling capability while maintaining a compact planar footprint. The raised extension regions extend upward from the substrate surface, allowing high voltage operation without increasing the lateral area occupied by each transistor.
Solution Approach 2:
The patent applies different doping characteristics to specific localized regions: the raised extension regions are lightly-doped to provide high breakdown voltage, while the source and drain regions are heavily-doped for efficient current conduction. This localized differentiation of doping quality allows each region to optimize its function without compromising the other, achieving both high reliability and compact size.
2Reliability
If larger transistor footprint is used, then high breakdown voltages can be handled, but space utilization decreases
Solution Approach 1:
By raising the extension regions vertically, the patent enables high breakdown voltage handling within a compact planar footprint, thereby improving space utilization. The vertical dimension provides the necessary voltage handling capability without consuming additional lateral space, allowing more transistors to be packed into the same area.
Solution Approach 2:
The patent changes the geometric parameter of the extension regions from planar to raised (increasing height), and adjusts the doping concentration parameters (lightly-doped in raised regions, heavily-doped in source/drain). These parameter changes enable high breakdown voltage handling while maintaining compact transistor dimensions for improved space utilization.
Data Source
AI summary
Methods of forming a transistor might include forming a dielectric overlying a semiconductor having a first conductivity type, forming a conductor overlying the dielectric, patterning the conductor and dielectric to define a gate stack of the transistor, forming a first extension region base and a second extension region base in the semiconductor, forming a first extension region riser overlying the first extension region base and forming a second extension region riser overlying the second extension region base, and forming a first source/drain region in the first extension region riser and forming a second source/drain region in the second extension region riser, wherein the first extension region base, the second extension region base, the first source/drain region, and the second source/drain region each have a second conductivity type different than the first conductivity type.