Raised Extrinsic Base BiCMOS Integration via Selective Epitaxy
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Solution Overview
Problem
Integrating high performance bipolar transistors into BiCMOS circuits without adversely affecting CMOS transistor performance and minimizing process complexity, as existing methods often introduce topographical variations and increase complexity.
Innovation Solution
A semiconductor structure with a self-aligned raised extrinsic base formed by selective epitaxy and a mesa structure, integrated into a BiCMOS circuit using shallow trench isolation and pad layers, which compensates for differential growth rates and eliminates the need for chemical mechanical planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chemical mechanical planarization (CMP) process is used to form raised extrinsic base, then bipolar transistor performance is improved, but device complexity and process steps increase
Solution Approach 1:
The patent extracts and removes the CMP process step from the fabrication sequence, replacing it with selective epitaxial growth that naturally forms the raised extrinsic base without requiring mechanical planarization. This eliminates the harmful effects of CMP while maintaining the desired structural outcomes.
Solution Approach 2:
The patent replaces the mechanical CMP process with a chemical epitaxial growth process. Instead of mechanically planarizing the surface, the invention uses selective epitaxial growth to form the raised extrinsic base, substituting a mechanical system with a chemical/thermal system that achieves the same functional result without the drawbacks.
2Adaptability or versatility
If polysilicon placeholder material and planarization are used to compensate height differences, then BiCMOS integration is enabled, but process complexity increases significantly
Solution Approach 1:
The patent removes the polysilicon placeholder material step and the associated planarization steps from the process flow. The selective epitaxial growth directly forms structures at appropriate heights without requiring placeholder materials, thereby eliminating these complexity-inducing steps while maintaining BiCMOS integration capability.
Solution Approach 2:
The patent uses selective epitaxial growth as an intermediary process that naturally bridges the height difference between bipolar and CMOS structures. Instead of using placeholder materials as intermediaries, the epitaxial growth process itself acts as the mediating mechanism that achieves proper alignment and height matching.
3Manufacturing precision
If additional lithographic patterning and planarization steps are used, then extrinsic base formation precision is improved, but manufacturing time and complexity increase
Solution Approach 1:
The patent employs self-aligned selective epitaxial growth where the extrinsic base automatically forms aligned with the emitter through the selective nature of the epitaxial process. The structure serves its own alignment function without requiring additional lithographic patterning steps, achieving high precision while reducing process time.
Solution Approach 2:
The patent performs preliminary selective epitaxial growth to form the raised extrinsic base before subsequent processing steps. This preliminary formation establishes the correct geometry and alignment early in the process, eliminating the need for later corrective patterning and planarization steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high performance bipolar transistors with reduced process complexity, maintaining CMOS device performance and achieving planar and vertical sidewall surfaces in the mesa structure.
Implementation Method 1
a raised extrinsic base formed by selective epitaxial growth
Data Source
AI summary
High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.