Raised Source/Drain Fin Straps for Multi-Fin FETs
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Solution Overview
Problem
Multi-fin field effect transistors face increased circuit delay and power consumption due to parasitic capacitance between the gate and source/drain straps, which degrades switching speed and efficiency.
Innovation Solution
The solution involves raising the level of source/drain straps above the gate and electrically connecting them using conductive vias or taller source/drain regions to minimize capacitance, while maintaining low resistance strapping of the source/drain regions in multi-fin field effect transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain straps are placed at the same level as the gate to provide low resistance strapping, then electrical connection is improved, but capacitance between gate and straps increases causing circuit delay and power consumption
Solution Approach 1:
The source/drain straps are raised to a higher elevation level above the gate, transitioning from a planar two-dimensional layout to a three-dimensional vertical arrangement. This dimensional change allows the straps to be positioned above the gate rather than at the same level, reducing parasitic capacitance while maintaining electrical connectivity through vertical vias that pass through the gate structure.
2Speed
If source/drain straps are raised above the gate level to reduce capacitance, then circuit speed is improved, but electrical connection complexity increases requiring additional vias or taller regions
Solution Approach 1:
Conductive vias serve as intermediary elements that bridge the vertical gap between the raised source/drain straps and the underlying fin structures. These vias act as mediators, passing through the gate region to establish electrical connection without requiring the straps to be at gate level, thus reducing capacitance while maintaining connectivity through an intermediate conductive pathway.
Solution Approach 2:
The fin structures are made taller in specific localized regions where source/drain straps need to be connected, rather than increasing the height of the entire fin uniformly. This local quality approach allows the straps to be raised above the gate level in specific areas while keeping other regions at standard height, reducing overall device complexity while achieving the capacitance reduction goal.
Data Source
AI summary
Therefore, disclosed above are embodiments of a multi-fin field effect transistor structure (e.g., a multi-fin dual-gate FET or tri-gate FET) that provides low resistance strapping of the source/drain regions of the fins, while also maintaining low capacitance to the gate by raising the level of the straps above the level of the gate. Embodiments of the structure of the invention incorporate either conductive vias or taller source/drain regions in order to electrically connect the source/drain straps to the source/drain regions of each fin. Also, disclosed are embodiments of associated methods of forming these structures.