Self-aligned memory structure with raised floating gates
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Solution Overview
Problem
Conventional non-volatile memory cells require high currents for operation, making them unsuitable for low-power devices, and their structure limits cell density and efficiency due to the alignment of floating gates with control gates, which restricts the reduction of memory cell size.
Innovation Solution
A symmetrical and self-aligned non-volatile memory structure is developed with a high cell density and improved coupling ratio, featuring conductive lines, dielectric spacers, and conductive blocks with raised tops and sides, allowing for perpendicular word lines and increased dielectric layer area to enhance floating gate voltage and reduce neighbor capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional non-volatile memory cells use traditional floating gate structures with control gate alignment, then the memory cell structure is simple to manufacture, but the cell density is limited and programming current remains high
Solution Approach 1:
The patent introduces a vertical dimension by forming raised conductive blocks with elevated tops and sides, creating a three-dimensional structure. The dielectric layer is positioned on the raised portions of the conductive blocks, utilizing vertical space to increase the coupling area between the control gate and floating gate without expanding the planar footprint. This dimensional transition enables higher cell density while maintaining low programming current through improved electrical coupling.
Solution Approach 2:
The patent implements a nested structure where the dielectric layer is positioned within the raised portions of the conductive blocks, and the control gate is formed over the dielectric layer. This nested arrangement maximizes the coupling ratio by placing the dielectric layer in close proximity to both the floating gate (conductive block) and control gate, enabling efficient charge transfer with minimal programming current while increasing cell density.
2Length of moving object
If the floating gate is aligned with the control gate in conventional structures, then the manufacturing process is straightforward, but the memory cell size cannot be reduced significantly
Solution Approach 1:
The patent employs asymmetric structure design where the conductive blocks have raised tops and sides that extend beyond the planar alignment with the control gate. The dielectric layer is positioned on these raised portions, creating an asymmetric charge storage region. This asymmetry allows the floating gate to be smaller than the control gate in the width direction while maintaining sufficient coupling area, enabling cell size reduction without requiring tight alignment tolerances.
Solution Approach 2:
The patent forms the conductive blocks with raised tops and sides before forming the control gate, establishing a pre-defined coupling region. The dielectric layer is deposited on the raised portions of the conductive blocks prior to control gate formation, ensuring that the coupling area is predetermined and does not depend on subsequent alignment steps. This preliminary structuring reduces sensitivity to alignment variations and enables smaller cell dimensions.
3Object-affected harmful factors
If conventional memory structures use standard dielectric layer positioning, then the neighbor capacitance is higher, but the structure is easier to manufacture
Solution Approach 1:
The patent applies local quality enhancement by positioning the dielectric layer specifically on the raised tops and sides of the conductive blocks, rather than uniformly across the entire conductive block surface. This localized dielectric placement concentrates the coupling capacitance in specific regions while reducing capacitance to neighboring cells. The raised structure creates physical separation between adjacent memory cells, reducing neighbor capacitance without significantly increasing overall structural complexity.
Data Source
AI summary
A memory structure formed between two doping regions in a semiconductor substrate includes two conductive blocks functioning as floating gates formed at two sides of a first conductive line functioning as a select gat and insulated from the first conductive line with two first dielectric spacers therebetween, wherein the two conductive blocks each have a raised top and raised parts of sides relative to the top of the first conductive line. A first dielectric layer is formed on the tops and the parts of the sides of the two conductive blocks. A second conductive line functioning as a word line is formed on the first dielectric layer, wherein the second conductive line has a part deposited between the two conductive blocks and is substantially perpendicular to the first conductive line and two doping region functioning as bit lines.