Non-Volatile Memory Array With Raised Floating Gates
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Solution Overview
Problem
Conventional non-volatile memory cells require high currents for operation, making them unsuitable for low-power devices, and existing EEPROM structures struggle to reduce cell size due to alignment tolerances between floating and select gates.
Innovation Solution
A memory array structure with raised floating gates and select gates, where the floating gates have a larger area for improved coupling ratio, and a method for reading that involves preprogramming thresholds and charging voltages to optimize current flow between data lines, reducing equivalent resistance and enhancing reading accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional non-volatile memory cells are used, then data storage capability is achieved, but high current requirements (200 μA) make them unsuitable for low-power devices
Solution Approach 1:
The gate structure is segmented into multiple polysilicon layers (first polysilicon layer for floating gate, second polysilicon layer for control gate, third polysilicon layer for erase gate), allowing independent optimization of each layer's function to reduce overall current requirements while maintaining programming efficiency
Solution Approach 2:
Different regions of the channel are doped with different conductivity types (P-type channel with N+ buried source/drain, or N-type channel with P+ buried source/drain), creating localized high-field regions that improve hot electron generation efficiency and reduce the current needed for programming
2Ease of manufacture
If floating gates are completely defined by control gates during patterning, then manufacturing simplicity is maintained, but floating gates must be larger than select gates which prevents significant memory cell size reduction
Solution Approach 1:
The floating gate is pre-formed before control gate patterning, allowing the control gate to be defined independently with tighter alignment tolerances. This preliminary formation of the floating gate structure enables subsequent precise patterning of the control gate without being constrained by alignment requirements
Solution Approach 2:
The patent introduces a vertical stacking dimension with multiple polysilicon layers (first, second, and third polysilicon layers at different heights), allowing the floating and control gates to be defined in different vertical planes. This dimensional separation eliminates the need for precise lateral alignment between floating and control gates, enabling smaller memory cell footprints
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure achieves reduced current requirements and improved memory cell density by increasing the coupling ratio and minimizing neighbor capacitance, allowing for accurate data reading with lower power consumption.
Implementation Method 1
the floating gates have a larger area for improved coupling ratio
Implementation Method 2
preprogramming a first right floating gate to a high threshold and a first left floating gate coupled to a same first word line as the first right floating gate to a low threshold
Implementation Method 3
charging a voltage of the right data line to a first predetermined value, charging a voltage of the first word line to a second predetermined value
Implementation Method 4
comparing a current of the left data line with a fourth predetermined value
Data Source
AI summary
A method for reading a memory array is disclosed. The method includes turning on the column of select gates; preprogramming a first right floating gate to a high threshold and a first left floating gate coupled to a same first word line as the first right floating gate to a low threshold; charging a voltage of the right data line to a first predetermined value; charging a voltage of the first word line to a second predetermined value which is between the high threshold of the first right floating gate and the low threshold of the first left floating gate; charging a voltage of a second word line coupled to a second right floating gate to a third predetermined value; and comparing a current of the left data line with a fourth predetermined value.