Raised LOCOS Insulation for Power CMOS Integration

Solution Overview

Problem

The integration of low-voltage and power devices on a semiconductor chip using conventional shallow-trench isolation (STI) techniques faces limitations, particularly with 0.25-μm and 0.18-μm technologies, leading to high and unstable active-state resistance (RON) and breakdown voltage (BV) issues due to the concentration of electrical-field lines and marked angles at the interface between thin and thick oxide regions.

Innovation Solution

The process involves creating raised LOCOS insulation regions through selective epitaxial growth and local thermal oxidation, which form less pronounced angles with the substrate, reducing the concentration of electrical-field lines and improving insulation without penetrating deeply into the substrate, thereby enhancing the reliability and performance of power components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If shallow-trench isolation (STI) technique is used to insulate active areas, then integration density is improved, but electrical-field concentration occurs at the interface causing high and unstable RON and BV

Engineering Contradiction:

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The isolation structure is segmented into multiple layers: a first insulation layer filling the trench with vertical walls, and a second insulation layer formed on top with controlled angles. This segmentation allows the first layer to provide isolation while the second layer mitigates field concentration, resolving the contradiction between integration density and reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the isolation structure are given different properties: the first insulation layer provides vertical isolation for high integration, while the second insulation layer provides angled surfaces specifically at the interface region to reduce field concentration. This local differentiation of properties allows simultaneous achievement of high integration and stable electrical characteristics.

Inventive Principle:

Principle #3Local quality

2Reliability

If STI trenches are etched deeply into the substrate, then insulation effectiveness is improved, but manufacturing complexity and cost increase

Engineering Contradiction:

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

A second insulation layer is introduced as an intermediary element between the substrate and the gate structure. This intermediate layer with its angled surfaces serves as a mediator that reduces electrical-field concentration without requiring deeper trench etching, thus improving insulation effectiveness while avoiding increased manufacturing complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Length of moving object

If vertical walls are formed in STI trenches to minimize transition area, then device dimensions are reduced, but electrical-field line concentration increases

Engineering Contradiction:

Core Design Contradiction:

Length of moving objectVSObject-affected harmful factors

Solution Approach 1:

The isolation structure employs asymmetric geometry: vertical walls in the first insulation layer for compact dimensions, and angled surfaces in the second insulation layer to distribute electrical fields. This asymmetric design allows small device dimensions while eliminating the harmful field concentration effect.

Inventive Principle:

Principle #4Asymmetry

Solution Approach 2:

The second insulation layer introduces curved or angled surfaces at the interface region, replacing the sharp vertical angles of the first layer. This curvature/angulation reduces the concentration of electrical-field lines by creating a more gradual transition, thereby reducing harmful field effects while maintaining compact dimensions.

Inventive Principle:

Principle #14Spheroidality (Curvature)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the limitations of STI by achieving more homogeneous electrical field distribution and minimizing the active-state resistance and breakdown voltage issues, making power components more reliable and efficient while maintaining the high integration and small dimensions of CMOS technology.

Implementation Method 1

selective epitaxial growth

Methodology Applied

Scientific EffectEpitaxial growth: Epitaxy

Implementation Method 2

local thermal oxidation

Methodology Applied

Scientific EffectThermal oxidation: Oxidation

Data Source

PatentUS8941176B2Integrated device with raised locos insulation regions and process for manufacturing such device

Publication Date: 2015.01.27

AI summary

An embodiment of an integrated device includes a semiconductor body, in which an STI insulating structure is formed, laterally delimiting first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. Formed in the second active area is a power component, which includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region, arranged between the body region and the drain-contact region and having a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion.