Raised Source/Drain Oxide TFT Structure for Lower Contact Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturizing transistors further due to high contact resistance between metal and thin film oxide semiconductors, which hampers the integration of thin film transistors (TFTs) in the back-end-of-line (BEOL) for increased areal density and functionality, as current TFTs have insufficient switching speed for core logic tasks.
Innovation Solution
The development of raised source/drain oxide semiconducting thin film transistors that combine the metallic properties of thick Indium-Tin-Oxide (ITO) layers with the semiconducting properties of thin ITO layers, utilizing a scalable architecture that does not require doping, to reduce parasitic resistance and improve contact quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If thin film oxide semiconductor layers are used in TFTs for BEOL integration, then low processing temperature is achieved, but high contact resistance occurs between metal and semiconductor
Solution Approach 1:
The patent applies local quality by creating a raised source/drain structure where the oxide semiconductor layer is thicker at the source/drain regions compared to the channel region. This localized thickness variation provides better metal-semiconductor contact at the source/drain regions (reducing contact resistance) while maintaining the thin channel thickness needed for low processing temperature and proper transistor operation.
2Area of stationary object
If transistor size is reduced to increase areal density, then chip area utilization improves, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent transitions from a two-dimensional planar transistor structure to a three-dimensional raised source/drain structure. By adding the vertical dimension with raised source/drain regions, the invention achieves better electrical contact and improved device performance without further reducing the lateral footprint, thus maintaining manufacturing precision while increasing areal density through vertical stacking.
3Speed
If oxide semiconductor layer thickness is reduced for better semiconducting properties, then switching speed improves, but contact resistance increases
Solution Approach 1:
The patent implements local quality by having different oxide semiconductor layer thicknesses in different regions: a thinner thickness in the channel region for fast switching and a thicker thickness at the source/drain regions for low contact resistance. This spatially varying thickness profile simultaneously optimizes both switching speed and contact quality.
Data Source
AI summary
A transistor, integrated semiconductor device and methods of making are disclosed. The transistor includes a patterned gate electrode, a dielectric layer located over the patterned gate electrode and a patterned first oxide semiconductor layer comprising a channel region and source/drain regions located on sides of the channel region. The thickness of the source/drain regions is greater than a thickness of the channel region. The transistor also includes contacts located on the patterned first oxide semiconductor layer and connected to the source/drain regions of the patterned first oxide semiconductor layer.