Raised S/D FET Halo Doping for Narrow Width Vt Control
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Solution Overview
Problem
Existing methods for fabricating nano-scale field-effect transistors (FETs) face challenges in maintaining threshold voltage (Vt) as devices are scaled down, leading to a decrease in Vt due to factors like gate oxide thinning, doping depletion, and stress effects, which prior art methods like STI optimization are unable to adequately address.
Innovation Solution
The method involves forming raised source/drain regions with a halo region created by implanting dopants at specific tilt and twist angles to increase the threshold voltage, particularly at the edges of the FET, allowing for control and adjustment of Vt in FETs with raised S/D regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If gate width is decreased to scale down devices, then device size is reduced, but threshold voltage decreases due to narrow width effect
Solution Approach 1:
The patent applies local quality by creating a non-uniform doping profile within the channel region. Specifically, higher doping concentrations are introduced near the source/drain junctions while maintaining lower doping in the channel center region. This localized doping variation compensates for the narrow width effect at the edges without degrading the channel transport properties, thereby maintaining threshold voltage in scaled devices.
Solution Approach 2:
The patent changes the doping concentration parameter spatially within the device structure. By implementing a doping profile that varies from high concentration near the junctions to low concentration in the channel center, the patent optimizes both threshold voltage control and carrier transport. This parameter variation allows the device to maintain performance at scaled dimensions.
2Reliability
If doping concentration is increased to increase threshold voltage, then threshold voltage increases, but series resistance increases
Solution Approach 1:
The patent applies local quality by spatially differentiating the doping concentration within the channel region. High doping concentrations are localized near the source/drain junctions where threshold voltage control is needed, while the channel center region maintains low doping concentrations to minimize series resistance. This localized approach allows independent optimization of threshold voltage and resistance characteristics.
Solution Approach 2:
The patent segments the channel doping into distinct regions with different doping concentrations. The channel is divided into a heavily doped region near the junctions and a lightly doped region in the center, allowing each segment to serve its specific function: threshold voltage control in the doped regions and low-resistance transport in the undoped center region.
3Reliability
If halo doping is applied uniformly across the channel, then threshold voltage increases, but doping depletion effect worsens in the channel center
Solution Approach 1:
The patent applies local quality by creating a non-uniform halo doping profile that concentrates dopants near the source/drain junctions while avoiding the channel center region. This localized doping provides threshold voltage control where needed (at the junctions) while preserving the doping concentration in the channel center, thereby preventing degradation of carrier transport properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the gate threshold voltage of narrow-width FETs to match or exceed that of wider devices, enabling the fabrication of smaller FETs with minimal Vt decrease and providing adjustable Vt control.
Implementation Method 1
A first halo region is formed by implanting dopants of the first conductivity type within the substrate
Data Source
AI summary
A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.