Raised Source/Drain Structures in NFET with Embedded SiGe Stressor

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The integration of raised source/drain (S/D) structures with embedded SiGe in Field Effect Transistors (FETs) is complicated, especially for PFETs with raised S/D structures in NFETs, due to additional process requirements and difficulties in protecting poly-Si gates, which hinders efficient device performance.

Innovation Solution

A method is developed to form raised S/D structures in NFETs with embedded SiGe in PFETs by creating recesses in the PFET region, forming an epitaxial SiGe stressor, and growing epitaxial Si layers over both regions, while using spacers and silicide formation to enhance device performance and reduce resistivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If embedded SiGe is integrated in PFET with raised S/D structures in NFET, then device performance is enhanced, but process complexity increases significantly

Engineering Contradiction:

Improvedevice performanceVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the CMOS device into separate NFET and PFET regions with distinct S/D structures. NFET regions receive raised S/D structures while PFET regions receive embedded SiGe, allowing each transistor type to be optimized independently through segmented processing steps

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different S/D structures are implemented in different locations: raised S/D structures are formed in NFET regions while embedded SiGe is formed in PFET regions. This local differentiation allows each region to have the optimal structure for its specific performance requirements

Inventive Principle:

Principle #3Local quality

2Reliability

If raised S/D structures are formed in NFET, then external resistance is reduced, but manufacturing complexity increases

Engineering Contradiction:

Improveexternal resistanceVSAvoidmanufacturing complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

S/D extension regions are formed before the raised S/D structures. These pre-formed extensions serve as templates and stressors that guide subsequent epitaxial growth, making the raised S/D formation process more controlled and manufacturable

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Epitaxial Si layers are grown over the S/D extension regions to form the raised S/D structures. The epitaxial growth process acts as an intermediary that transforms the pre-formed extensions into the final raised structures with controlled dimensions and properties

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If embedded SiGe is formed in PFET, then sheet resistance is reduced, but poly-Si gate protection becomes difficult

Engineering Contradiction:

Improvesheet resistanceVSAvoidgate protection

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies different material compositions and structures to different regions: PFET regions contain embedded SiGe for low sheet resistance while NFET regions have standard structures. This local differentiation allows optimized electrical properties without compromising gate integrity across the entire device

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The processing is segmented into PFET-specific and NFET-specific steps. Embedded SiGe formation is applied only to PFET regions where it is needed, while NFET regions proceed with standard processing, thereby avoiding gate protection issues in NFET while achieving low resistance in PFET

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for stable and low-resistivity silicide formation, improves device performance by reducing external resistance and S/D sheet resistance, and facilitates integration of both raised and embedded SiGe structures, enhancing the overall performance of FETs.

Implementation Method 1

forming an epitaxial SiGe stressor in the recesses

Methodology Applied

Scientific EffectStress:

Implementation Method 2

growing epitaxial Si layers over both regions

Methodology Applied

Scientific EffectEpitaxy: Epitaxy

Implementation Method 3

implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D epitaxial Si layer

Methodology Applied

Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS7718500B2Formation of raised source/drain structures in NFET with embedded SiGe in PFET

Publication Date: 2010.05.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.