Raised SiGe Extension Region for PMOS Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The difference in dopant diffusion properties between silicon and silicon germanium (SiGe) layers in PMOS devices leads to uneven source/drain junction spacing, increasing leakage in PMOS transistors due to faster Boron diffusion in silicon layers compared to SiGe layers.
Innovation Solution
A method is developed to form a raised, in-situ doped extension region over a compressively strained SiGe layer, reducing dopant diffusion below the channel region and using a faceted structure to slow down dopant diffusion from the SiGe layer, thereby maintaining consistent source/drain junction spacing and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a strained SiGe epitaxial layer is formed over silicon at PMOS channel regions to increase hole mobility, then hole mobility is improved, but source/drain junction spacing becomes uneven due to different dopant diffusion rates in Si and SiGe layers
Solution Approach 1:
The patent applies local quality by forming a silicon cap layer selectively over the SiGe channel region where dopant diffusion needs to be enhanced. The cap layer is positioned locally at the source/drain extension regions rather than uniformly across the entire device, allowing differential dopant diffusion control in different spatial locations to achieve uniform junction spacing while maintaining SiGe-induced hole mobility enhancement
Solution Approach 2:
The silicon cap layer acts as an intermediary between the SiGe channel and the implanted dopant atoms. This intermediate silicon layer modulates the dopant diffusion process by providing a diffusion pathway that equalizes the effective diffusion rate between SiGe and silicon regions, thereby mediating the conflicting diffusion behaviors to achieve uniform source/drain junction spacing
2Object-generated harmful factors
If in-situ doped extension regions are formed to reduce leakage, then leakage current is reduced, but dopant diffusion control becomes complex due to multiple materials with different diffusion properties
Solution Approach 1:
The patent applies parameter changes by controlling the thickness of the silicon cap layer to precisely modulate dopant diffusion. By adjusting the cap layer thickness parameter, the effective diffusion rate is controlled to achieve uniform source/drain junction spacing while reducing leakage current, simplifying the overall diffusion control process despite the presence of multiple materials
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by reducing leakage current, enhancing short channel control, and maintaining better mobility and capacitance compared to previous methods.
Implementation Method 1
diffusion of implanted Boron below the PMOS gate occurs at a faster rate in the Silicon layer than in the SiGe layer
Implementation Method 2
using a faceted structure to slow down dopant diffusion from the SiGe layer
Data Source
AI summary
A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate structure to a location underlying the gate structure. A non-diffusing activation process can be used to activate source/drain implants when the dopants from the raised region are diffused prior to deep source/drain implantation.