Self-Aligned Contacts for Raised Source Drain CMOS Structures
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Solution Overview
Problem
The leading edge CMOS industry faces challenges in lithographic scaling for nodes beyond 10 nm due to high process complexity and costs, particularly in forming contacts to raised sources and drains, where high-k gate dielectrics are used to scale down the gate dielectric thickness.
Innovation Solution
A method for forming self-aligned contacts to raised sources and drains in CMOS structures involves providing a substrate with a channel layer, forming a gate stack structure, creating sidewall spacers, depositing an insulating dielectric layer, planarizing it, selectively etching the spacers to create contact cavities, and filling these cavities with contact plugs, thereby reducing the need for high-resolution lithography and lowering fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If high-k gate dielectrics are used to scale down gate dielectric thickness, then gate dielectric thickness is reduced, but process complexity and fabrication costs increase
Solution Approach 1:
The contact formation process is segmented into distinct stages: forming mandrels, depositing first spacers, forming raised sources/drains, depositing second spacers, and selective removal. This segmentation allows each step to be optimized independently and simplifies the overall complex process by breaking it into manageable, self-aligned stages.
Solution Approach 2:
Sidewall spacers are formed preliminarily on the gate stack before contact hole formation. This preliminary action establishes precise alignment references that guide subsequent contact opening steps, eliminating the need for additional lithography alignment operations and reducing overall process complexity.
2Manufacturing precision
If conventional lithography is used for contact formation at advanced nodes, then contact alignment is achieved, but fabrication costs and process complexity increase
Solution Approach 1:
The sidewall spacers serve as self-aligned masks that automatically define contact hole positions based on gate stack geometry. This self-service mechanism eliminates the need for external lithography alignment operations, as the spacers themselves generate the precise alignment references needed for contact formation.
Solution Approach 2:
Sidewall spacers act as intermediary structures between the gate stack and the final contact holes. These spacers mediate the alignment process by providing physical reference surfaces that guide contact opening, replacing the need for complex lithographic alignment at advanced nodes.
3Reliability
If raised sources and drains are formed, then series resistance is reduced, but contact formation complexity increases
Solution Approach 1:
The solution moves from planar contact formation to three-dimensional self-aligned contact formation using vertical sidewall spacers. By utilizing the vertical dimension and the existing raised source/drain topography, the method creates contact holes that are automatically aligned to the raised regions, reducing series resistance while managing complexity through dimensional transition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of self-aligned contacts with reduced series resistance and lower fabrication costs, simplifying the process complexity associated with advanced node scaling without requiring high-resolution lithography, thus addressing the limitations in contact formation at advanced nodes.
Implementation Method 1
depositing an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers
Implementation Method 2
planarization of the insulating dielectric layer
Implementation Method 3
selectively etching the second sidewall spacers. Thereby contact cavities are created above the raised source and the raised drain
Data Source
AI summary
The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.