Raised Source Drain Epitaxy for Semiconductor Resistance Reduction
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Solution Overview
Problem
The increasing trend towards smaller device sizes in semiconductor manufacturing has resulted in higher source/drain resistance due to decreased contact size, necessitating a method to reduce source/drain resistance in transistors.
Innovation Solution
A semiconductor device with a conductive gate structure overlying a semiconductor layer, featuring a shallow trench isolation structure with an epitaxial layer formed on the source/drain regions to create raised source/drain areas, reducing resistance and improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device sizes are reduced to increase integration density, then productivity and device density improve, but source/drain resistance increases due to decreased contact size
Solution Approach 1:
The patent applies dimensionality change by forming raised source/drain regions that extend vertically from the substrate surface. The epitaxial layer is grown to create elevated contact regions, transforming the traditional planar contact geometry into a three-dimensional structure. This vertical extension increases the effective contact area without increasing the lateral device footprint, thereby maintaining high device density while reducing source/drain resistance through enhanced current flow pathways.
Solution Approach 2:
The patent implements local quality by selectively forming raised regions only at the source and drain contact areas, while maintaining the original substrate level in the channel and isolation regions. The epitaxial layer is grown selectively on exposed semiconductor surfaces at the source/drain regions, creating localized structural modifications that improve electrical characteristics at specific locations without affecting other parts of the device.
2Manufacturing precision
If shallow trench isolation structures are used to define source/drain regions, then device separation and manufacturing precision improve, but source/drain resistance increases due to smaller contact dimensions
Solution Approach 1:
The patent overcomes the resistance issue caused by small contact dimensions by extending the source/drain regions vertically. The raised structures create additional current flow pathways in the vertical dimension, compensating for the reduced lateral contact area. This allows the shallow trench isolation to maintain its precision in defining device boundaries while the elevated contacts provide sufficient electrical conductivity.
Solution Approach 2:
The patent segments the source and drain regions into multiple levels by forming raised portions that extend above the substrate surface. This segmentation creates distinct electrical pathways: the elevated regions provide low-resistance contact areas, while the isolation structures maintain precise device separation. The segmented structure allows independent optimization of electrical performance and geometric precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively lowers source/drain resistance and enhances transistor performance by forming epitaxial layers on the source/drain regions within the shallow trench isolation structure, improving the electrical characteristics of semiconductor devices.
Implementation Method 1
An epitaxial layer is formed on exposed portions of the source/drain major surface and sidewall
Data Source
AI summary
A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.