Raised Source/Drain Structure With Vertical Epitaxy to Prevent Merging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor technology faces challenges in reducing contact resistance in transistors, leading to increased transistor delay, and the raised source/drain (RSD) structures are susceptible to volume loss and merging during fabrication, causing electrical leakage and IC failure due to reduced pitches.
Innovation Solution
A source/drain (S/D) structure with reduced lateral extension and enhanced vertical extension is implemented, utilizing an epitaxial growth process with varying growth temperatures to achieve a higher growth rate vertically than laterally, reducing RSD loss and merging, and maintaining sufficient channel stress for improved transistor speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If raised source/drain (RSD) structures are used to reduce contact resistance, then transistor speed is improved, but volume loss and merging occur during fabrication
Solution Approach 1:
The patent applies parameter changes by varying the growth temperature during epitaxial growth to control the growth rate anisotropy. By reducing growth temperature, the process achieves higher vertical growth rate relative to lateral growth rate, which maintains RSD structure volume and prevents merging while preserving the low contact resistance benefit for transistor speed.
Solution Approach 2:
The patent exploits dimensional control by enhancing vertical extension of the RSD structure through anisotropic growth while suppressing lateral extension. This dimensional differentiation allows the structure to maintain sufficient volume for electrical performance while avoiding lateral merging with adjacent structures during fabrication.
2Loss of substance
If growth temperature is reduced to increase vertical growth rate, then RSD loss is reduced, but manufacturing precision control becomes more difficult
Solution Approach 1:
The patent changes the growth temperature parameter to a reduced range that inherently provides anisotropic growth characteristics. This temperature parameter change creates a natural preference for vertical growth over lateral growth, reducing RSD volume loss while the self-aligning nature of the anisotropic growth simplifies rather than complicates precision control.
Solution Approach 2:
The epitaxial growth process at reduced temperature exhibits self-service behavior where the anisotropic growth rate automatically directs material deposition preferentially in the vertical direction. This self-organizing growth pattern reduces reliance on complex external control mechanisms and naturally minimizes lateral RSD loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces RSD loss and merging, enhancing transistor speed and yield by maintaining sufficient channel stress and minimizing contact resistance, thereby improving the performance and reliability of integrated circuits.
Implementation Method 1
formed through epitaxial growth
Data Source
AI summary
The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, and a source/drain (S/D) region adjacent to the gate structure. The S/D region can include first and second side surfaces separated from each other. The S/D region can further include top and bottom surfaces between the first and second side surfaces. A first separation between the top and bottom surfaces can be greater than a second separation between the first and second side surfaces.