Nonvolatile Memory With Raised Source And Drain Regions
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Solution Overview
Problem
Conventional nonvolatile nitride memory cell structures face issues with scalability, high power program and erase operations, and high sheet resistance due to their planar structure.
Innovation Solution
The introduction of a nonvolatile memory cell integrated circuit with a charge trapping structure, source and drain regions separated by a channel region, and dielectric structures that isolate parts of the circuit, where the channel region is either recessed or the source and drain regions are raised, enhancing the interface between the charge trapping structure and the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar structure is used for nonvolatile nitride memory cell structures, then the manufacturing process is simple, but scalability is poor and sheet resistance is high
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a three-dimensional structure by raising the source and drain regions vertically. This dimensional change allows for better scalability while maintaining manufacturing feasibility, as the raised regions create improved interfaces with the charge trapping layer without requiring complex manufacturing processes
2Ease of manufacture
If a planar structure is used for nonvolatile nitride memory cell structures, then the manufacturing process is simple, but power consumption for program and erase operations is high
Solution Approach 1:
By raising the source and drain regions into three-dimensional structures, the patent creates better interfaces with the charge trapping layer. This improved interface geometry enhances charge trapping efficiency, which reduces the power required for program and erase operations while keeping the manufacturing process relatively simple
3Device complexity
If a planar structure is used for nonvolatile nitride memory cell structures, then the device structure is simple, but sheet resistance is high
Solution Approach 1:
The patent raises the source and drain regions vertically to create three-dimensional structures with improved interfaces to the charge trapping layer. This dimensional change enhances charge storage efficiency and reduces sheet resistance, while the overall device structure remains relatively simple and manufacturable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves scalability and reduces power requirements for program and erase operations, leading to more efficient data storage and retrieval in memory cells.
Implementation Method 1
These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases.
Implementation Method 2
The dielectric structures electrically isolate parts of the circuit from each other, in the absence of an electrical field to overcome the dielectric structures.
Data Source
AI summary
A nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region is included.