Raised Source/Drain Transistors With Simultaneous PFET-NFET Formation
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Solution Overview
Problem
The fabrication of integrated circuits (ICs) involving p-channel FETs (PFETs) and n-channel FETs (NFETs) requires separate and sequential process steps for forming raised source/drains, which is inefficient and increases the overall complexity and number of manufacturing steps.
Innovation Solution
Simultaneous formation of raised source/drains for both PFETs and NFETs using embedded silicon germanium (SiGe) regions for PFETs and silicon carbide (SiC) regions for NFETs, which exert compressive and tensile stress respectively to enhance hole and electron mobility, thereby reducing the number of process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate and sequential process steps are used to form raised source/drains for PFETs and NFETs, then device performance can be maintained, but the number of manufacturing steps increases and fabrication efficiency decreases
Solution Approach 1:
The patent merges the formation of raised source/drain structures for PFETs and NFETs into a single simultaneous annealing process step. By applying a unified thermal treatment that activates dopants in both p-type and n-type regions concurrently, the invention eliminates the need for separate sequential processing steps, thereby reducing manufacturing complexity and improving fabrication efficiency without compromising device performance
2Device complexity
If simultaneous formation of raised source/drains is used for both PFETs and NFETs, then the number of process steps is reduced, but process control complexity increases
Solution Approach 1:
The patent employs parameter changes by utilizing different thermal activation characteristics of p-type and n-type dopants. By carefully controlling the annealing temperature and duration parameters, the process achieves simultaneous activation of both dopant types with a single thermal cycle, thereby simplifying the overall process steps while maintaining ease of manufacture through well-established thermal processing techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of process steps and maintains device performance by enhancing mobility, thus optimizing the fabrication process for both PFETs and NFETs.
Implementation Method 1
embedded silicon germanium (SiGe) regions for PFETs and silicon carbide (SiC) regions for NFETs, which exert compressive and tensile stress respectively to enhance hole and electron mobility
Implementation Method 2
embedded silicon germanium (SiGe) regions for PFETs and silicon carbide (SiC) regions for NFETs, which exert compressive and tensile stress respectively to enhance hole and electron mobility
Data Source
AI summary
Transistors with raised source/drain structures and methods of making the transistors are described. A method for making such transistors includes forming a first gate and a second gate on a substrate, forming a p-doped region adjacent the first gate, and forming an n-doped region adjacent the second gate. The method further includes forming a silicon germanium (SiGe) region in a portion of the p-doped region. Subsequently, the method simultaneously forms raised source-drain structures over the SiGe region and on the n-doped region.